Packet Timestamping and CRC Verification for ISR Time Sync
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Solution Overview
Problem
ISR systems face limitations in data integrity and time synchronization across multiple platforms due to physical network interface restrictions and non-standard processor configurations, which hinder system performance and timing synchronization.
Innovation Solution
A multi-processor computer system with a remote node and control node, utilizing co-processors to verify data integrity through CRC values and synchronize timestamps, ensuring data integrity and time synchronization across multi-domain operational platforms via high-speed serial interfaces and specific data transfer protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical network interfaces are used to connect processors in ISR systems, then data transmission can be established, but the available locations of processors are restricted and timing synchronization is limited
Solution Approach 1:
A packet-based communication protocol is introduced as an intermediary layer between processors. The protocol includes packet headers with timestamps and CRC values, allowing processors to communicate reliably regardless of physical location or network interface limitations, thus resolving the contradiction between data integrity and location flexibility
2Adaptability or versatility
If standard communication protocols are used across different processor configurations, then interoperability is achieved, but non-standard processor configurations cannot utilize common architectural elements
Solution Approach 1:
The packet protocol is designed with universal applicability across different processor configurations. The standardized packet structure with universal fields (timestamp, CRC, data payload) allows any processor configuration to participate in the communication system without requiring matching architectural elements, resolving the contradiction between adaptability and complexity
3Reliability
If CRC verification is implemented for every data packet, then data integrity is ensured, but processing time and computational overhead increase
Solution Approach 1:
CRC values are pre-calculated and embedded in packet headers before transmission. The receiving processor can immediately verify data integrity using the pre-computed CRC without requiring complex real-time computation, thus ensuring data integrity while minimizing processing time overhead
Data Source
AI summary
A computer system is provided that includes devices configured to acquire input data. The system further includes a remote node (RN) configured to receive a first packet from a control node (CN). The first packet includes a packet header including a master timestamp, first control data and a CRC. The RN is also configured to verify integrity of the first control data based on the received CRC, generate and transmit to the CN a second packet. The second packet includes a packet header which includes a remote timestamp. The system also includes a CN connected with the RN via high-speed serial interfaces. The CN is configured to receive the second packet, determine status of the first packet based on the control data included in the second packet and configured to retransmit the first packet or generate and transmit a third packet based on the determined status of the first packet.