Packet Transfer Buffer Offloads Software Bandwidth
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Solution Overview
Problem
Conventional packet handling software in computer systems requires repetitive and time-consuming operations to transfer packets between source and destination interfaces, consuming many clock cycles due to the need for word-by-word movement and manual packet length verification.
Innovation Solution
A hardware-based packet data transfer buffer with source and destination FIFOs, an indexed packet array, and packet length counters, which offloads software tasks by using a packet state machine to manage packet transfer, allowing packets to be moved at a rate of one word per clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If packet handling software moves words one-by-one from source FIFO to destination FIFO, then packet transfer can be completed, but the process consumes many clock cycles and reduces transfer speed
Solution Approach 1:
The patent replaces the mechanical software-based word-by-word transfer mechanism with a hardware-based packet transfer buffer that uses FIFO (first-in-first-out) structures and control logic to automatically transfer packets. This substitution eliminates the need for software to manually move each word, thereby reducing clock cycle consumption and increasing transfer speed.
Solution Approach 2:
The patent introduces a packet transfer buffer as an intermediary hardware component between the source and destination interfaces. This buffer includes source and destination FIFOs that temporarily store packet data, allowing continuous data flow without requiring software intervention for each word transfer, thus improving productivity while reducing time loss.
2Ease of operation
If software performs repetitive word-by-word packet transfer operations, then packet data can be moved between interfaces, but software bandwidth requirements increase significantly
Solution Approach 1:
The patent extracts the packet transfer operation from the software domain and implements it in hardware. The packet transfer buffer independently handles the repetitive word-by-word transfer tasks, freeing software from these bandwidth-intensive operations and improving both ease of operation and software efficiency.
Solution Approach 2:
The packet transfer buffer is designed to autonomously manage packet transfers between source and destination interfaces using hardware-controlled FIFO structures. This self-service capability eliminates the need for software to continuously monitor and manage each transfer operation, reducing software bandwidth requirements while maintaining high productivity.
3Reliability
If manual software verification of packet length is performed, then packet transfer accuracy can be ensured, but the process becomes time-consuming
Solution Approach 1:
The patent replaces manual software verification with hardware-based packet length counters that automatically track and verify packet lengths during transfer. This substitution maintains transfer accuracy through reliable hardware counting while eliminating the time-consuming nature of software-based verification.
Data Source
AI summary
A packet transfer buffer for use in a computer system having multiple source and destination interfaces, as well as packet handling software. The buffer has a source packet FIFO and destination packet FIFO, each with an associated packet length counter. The packet handling software obtains packet lengths from the source packet counter, and provides the packet length to the destination packet counter. The buffer has hardware circuitry that handles transfer of data from the source packet FIFO to the destination packet FIFO without the need for word-by-word reads and writes by the packet handling software.