Packet Transmission Descriptor Timing Control

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Solution Overview

Problem

Conventional network arrangements require larger buffer memory allocation to prevent overflow, leading to inefficient memory usage due to the need to account for worst-case scenarios in packet transmission timing, resulting in suboptimal allocation and potential power inefficiencies.

Innovation Solution

The use of descriptors that specify exact transmission times for packets allows for more precise control over packet transmission timing, enabling the reduction of buffer memory allocation to match actual transmission bandwidth needs, thereby optimizing memory usage and allowing for continued power-saving techniques.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If buffer size is increased to prevent overflow in worst-case scenarios, then reliability of packet reception is improved, but memory usage efficiency deteriorates

Engineering Contradiction:
Improvepacket reception reliabilityVSAvoidbuffer memory allocation
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent changes the parameter of buffer sizing from fixed worst-case allocation to dynamic allocation based on actual transmission timing patterns. By modifying how buffer size is determined (from static maximum to dynamic actual-need-based), the system achieves both reliability and memory efficiency

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The transmitting host provides feedback information about actual packet transmission timing to the receiving host. This feedback enables the receiving host to adjust buffer allocation to match actual transmission patterns rather than relying on worst-case assumptions, resolving the contradiction between reliability and memory efficiency

Inventive Principle:
Principle #23Feedback

2Productivity

If average packet transmission timing is controlled to maintain predictable data rate, then network performance is improved, but actual transmission timing variability increases

Engineering Contradiction:
Improvedata transmission rate predictabilityVSAvoidpacket transmission timing variability
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the transmission timing control into two parts: average timing control (for predictable data rate) and individual packet timing information (for precise buffer management). By separating these concerns and providing both levels of timing information, the system achieves predictable throughput while enabling precise buffer allocation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces new parameters in the descriptor (such as transmission timestamp, sequence number, and timing deviation) that capture actual transmission timing information. This parameter enrichment allows the receiving host to precisely track when packets will arrive, reducing timing variability effects

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9405719B2Circuitry to generate and/or use at least one transmission time in at least one descriptor
Publication Date: 2016.08.02 INTEL CORP
  • US9405719B2 patent drawing
  • US9405719B2 patent drawing
  • US9405719B2 patent drawing

AI summary

An embodiment may include circuitry that may generate and/or use, at least in part, at least one descriptor to be associated with at least one packet. The at least one descriptor may specify at least one transmission time at which the at least one packet is to be transmitted. The at least one transmission time may be specified in the at least one descriptor in such a manner as to permit the at least one transmission time to be explicitly identified based at least in part upon the at least one descriptor. Many alternatives, modifications, and variations are possible without departing from this embodiment.