Transaction Packet Tunneler for Host Device Resource Access
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Solution Overview
Problem
Conventional methods for enabling peripherals to access host device resources through host bus adapters introduce latency and processing overhead due to address translation and caching, particularly when accessing internal resources behind a 'blind spot' in the host device's memory space.
Innovation Solution
The implementation of a transaction packet tunneler that determines the resource access intent based on packet identifiers, allowing direct routing to the host device or internal resources without address modification, thereby bypassing intermediate caching and translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If address translation and windowing are used to access host device resources behind a blind spot, then access to the entire memory space is enabled, but latency and processing overhead increase
Solution Approach 1:
The patent segments the address space into two distinct regions: a first address space region mapped to the peripheral device's internal cache memory, and a second address space region corresponding to the host device's memory space. By creating this segmentation, the system can route transactions differently based on the target address region, allowing direct access to the host memory space without requiring address translation or windowing operations, thereby reducing latency while maintaining access to the entire memory space.
2Adaptability or versatility
If internal cache memory is mapped to downstream peripheral device, then connectivity is expanded, but blind spot is created in host device's memory space
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a bridge or switch that receives transactions from the host device and routes them based on the target address. This intermediary enables the system to maintain the mapping of internal cache memory to the peripheral device while simultaneously allowing access to the host device's memory space. The intermediary translates and forwards transactions appropriately, resolving the blind spot issue without requiring complex memory space remapping or address translation schemes.
3Adaptability or versatility
If concurrent transactions require address translation and windowing, then resource access is enabled, but subsequent transactions must wait for previous transactions to complete
Solution Approach 1:
The patent segments the address space into distinct regions, allowing the system to identify and route transactions to the host device's memory space directly without requiring address translation or windowing operations. This segmentation enables concurrent transactions to proceed simultaneously to different address regions, eliminating the waiting behavior that occurs when transactions must sequentially acquire and release translated address windows, thereby improving transaction throughput while maintaining resource access capability.
Data Source
AI summary
The present disclosure describes apparatuses and techniques for tunneling transaction packets. In some aspects a packet is received from a peripheral device via a first data interface of a device. The packet includes an address for resource access and an identifier that identifies the peripheral device or a function thereof. Based on this identifier, it is determined whether the peripheral device is attempting to access an internal resource of the device or a resource of a host device connected to a second data interface of the device. If the peripheral device is attempting to access the resource of the host device, the packet is routed to the host device via the second data interface without modifying the address for resource access. By so doing, the peripheral device can exchange data with the host device without using address translation.