Packet Work Area Virtual Storage via Translation Unit
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Solution Overview
Problem
Network processors face challenges in manipulating packet data efficiently, as existing methods fail to provide a contiguous memory area for packet data and control information, necessitating a mechanism for mapping packet data into a processor's address space to enable normal load and store instructions through the cache.
Innovation Solution
A method and apparatus for implementing virtual packet storage via a packet work area, utilizing a mapping area with packet segment registers and a packet translation unit that maps packet data into a contiguous area, redirecting loads and stores into the correct data buffers in system memory, allowing software to access packet data without concern for hardware buffer sizes or allocation mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If packet data is stored in scattered memory locations using hardware buffers, then packet data can be manipulated, but normal load and store instructions through the cache cannot be used efficiently
Solution Approach 1:
The patent introduces a packet translation unit as an intermediary component that sits between the scattered hardware buffers and the processor's cache. This translation unit intercepts normal load and store instructions, translates the virtual packet addresses to actual buffer locations, and redirects the memory accesses accordingly. This allows software to use standard caching mechanisms while the translation unit handles the complexity of scattered buffer storage transparently.
Solution Approach 2:
The patent segments the packet storage system into multiple hardware buffers, each capable of holding portions of packet data. The packet translation unit maintains mappings between virtual packet addresses and these segmented buffer locations. This segmentation allows efficient utilization of available memory resources while maintaining the ability to access packet data through a unified virtual address space.
2Ease of operation
If a contiguous memory area is provided for packet data, then normal load and store instructions can be used, but the system must map scattered packet data into this contiguous area
Solution Approach 1:
The packet translation unit serves as the intermediary that handles the mapping complexity. It contains translation logic that converts virtual addresses in the contiguous packet work area to physical addresses in the scattered hardware buffers. This isolation of mapping complexity within a dedicated unit keeps the rest of the system simple while enabling efficient cache access.
Solution Approach 2:
The patent creates a virtual copy of the packet data layout in the packet work area that mirrors the logical structure of the packet, while the actual physical data resides in scattered buffers. The translation unit maintains this virtual-to-physical mapping, allowing software to operate on the virtual copy using simple addresses while the system handles the physical scattering transparently.
3Quantity of substance
If multiple packets share data buffers, then memory efficiency improves, but tracking and managing buffer descriptors becomes more complex
Solution Approach 1:
The packet translation unit implements feedback mechanisms where buffer descriptors are updated and tracked as packets are processed. When packets share buffers, the translation unit maintains reference counts and validation information in the buffer descriptors, providing feedback about buffer usage status. This allows the system to manage shared buffers efficiently while keeping track of which packets are using which buffer segments.
Data Source
AI summary
A method, apparatus and computer program product are provided for implementing virtual packet storage via packet work area (PWA) in a network processor system. A mapping area including a packet work area and a corresponding set of packet segment registers (PSRs) are provided. A PSR is loaded with a Packet ID (PID) and a packet translation unit maps the packet data into the corresponding PWA. The PWA address defining an offset into the packet is translated into a physical address. The packet translation unit redirects loads and stores of the PWA into the correct data buffer or buffers in system memory. Packets include one or more data buffers that are chained together, using a buffer descriptor providing the packet physical address. The buffer descriptor points to a data buffer for the packet and to a next buffer descriptor.