Packet Work Order Module for Multi-Core Network Processor Scheduling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current networking systems face performance limitations in processing upper network protocol layers (L4-L7) at wire-speed due to insufficient compute performance, particularly with compute-intensive tasks like checksum calculation and timer management in general-purpose processors.
Innovation Solution
A network services processor with a packet work order module that schedules and queues packet processing operations for L4-L7 protocols, allowing parallel execution by multiple processors with tag-based ordering and synchronization, and expanding input queues into external memory to prevent stalling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose processors are used to process L4-L7 network protocols, then intelligent processing capability is improved, but processing speed deteriorates and cannot achieve wire-speed forwarding
Solution Approach 1:
The network processor is segmented into multiple specialized processing units including a packet work order module, multiple in-flight lists, and parallel processors. Each unit handles specific tasks (queuing, scheduling, processing) to distribute the computational load and achieve both intelligence and high-speed processing.
Solution Approach 2:
The system dynamically schedules work packets across multiple processors based on current system state and packet characteristics. The packet work order module adapts its scheduling decisions in real-time to optimize processing throughput while maintaining wire-speed forwarding capability.
2Device complexity
If the input queue size is limited, then device complexity is reduced, but packet processing throughput deteriorates when the processor is busy
Solution Approach 1:
The input queue is extended into external memory space, transitioning from a limited on-chip queue to a virtually unlimited off-chip queue. This dimensional extension allows the queue to appear infinite to the packet work order module while maintaining simple queue management logic.
Solution Approach 2:
A queue extension mechanism acts as an intermediary between the limited on-chip queue and the external memory. This intermediary allows work packets to be staged in external memory and transferred to the processing pipeline as slots become available, preventing throughput degradation during high-load conditions.
3Productivity
If multiple processors execute work in parallel, then processing throughput is improved, but execution ordering and synchronization become more difficult
Solution Approach 1:
The packet work order module performs preliminary scheduling of work packets to specific processors before execution. By pre-assigning packets and establishing execution order in advance, the system enables parallel processing while maintaining deterministic ordering without requiring complex runtime synchronization mechanisms.
Solution Approach 2:
The system uses feedback from processor completion status and queue state to dynamically adjust scheduling decisions. The packet work order module monitors processor availability and work completion, using this feedback to maintain proper execution ordering while maximizing parallel throughput.
Data Source
AI summary
A method and apparatus for ordering, synchronizing and scheduling work in a multi-core network services processor is provided. Each piece of work is identified by a tag that indicates how the work is to be synchronized and ordered. Throughput is increased by processing work having different tags in parallel on different processor cores. Packet processing can be broken up into different phases, each phase having a different tag dependent on ordering and synchronization constraints for the phase. A tag switch operation initiated by a core switches a tag dependent on the phase. A dedicated tag switch bus minimizes latency for the tag switch operation.