Packetized Clock Generation for Multi-Rate Optical Networks
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Solution Overview
Problem
Packet optical communication networks face challenges in accommodating multiple clients with different data transmission rates, as they require separate analog phase locked loop (PLL) clock chips, which increase costs and occupy valuable space on printed circuit boards, particularly in high-rate devices.
Innovation Solution
The solution involves a packet interface that receives flow credit packets containing data rate information for each data flow, which are then forwarded to clock generators to produce corresponding clock signals, eliminating the need for separate clock chips by managing data rates in the digital domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate analog PLL clock chips are used to manage multiple data rates, then the network device can accommodate multiple clients with different transmission rates, but the cost and space requirements increase
Solution Approach 1:
The patent merges the clock generation functionality into the main network device chip by integrating multiple digital clock generators that can be configured through packetized commands. This eliminates the need for separate analog PLL clock chips, thereby reducing PCB space while maintaining the ability to support multiple data rates through software-controlled clock configuration
Solution Approach 2:
The main network device chip is designed to perform multiple functions including data processing, packet handling, and clock generation for multiple data rates. The digital clock generators can be dynamically configured to support different transmission rates, making the chip universal rather than requiring dedicated clock chips for each rate
2Adaptability or versatility
If separate analog PLL clock chips are used to manage multiple data rates, then the network device can accommodate multiple clients with different transmission rates, but the cost increases
Solution Approach 1:
The patent merges the clock generation functionality into the main network device chip by integrating multiple digital clock generators that can be configured through packetized commands. This eliminates the need for separate analog PLL clock chips, thereby reducing PCB space while maintaining the ability to support multiple data rates through software-controlled clock configuration
Solution Approach 2:
The main network device chip is designed to perform multiple functions including data processing, packet handling, and clock generation for multiple data rates. The digital clock generators can be dynamically configured to support different transmission rates, making the chip universal rather than requiring dedicated clock chips for each rate
3Ease of repair
If separate clock chips are used, then fault isolation and replacement is simplified through FRU design, but the device requires more space for these additional components
Solution Approach 1:
The patent merges the clock generation functionality into the main network device chip by integrating multiple digital clock generators that can be configured through packetized commands. This eliminates the need for separate analog PLL clock chips, thereby reducing PCB space while maintaining the ability to support multiple data rates through software-controlled clock configuration
Data Source
AI summary
Systems, apparatus, and methods for packetized clocks may include a packet interface to carry the rate of a client to a sigma-delta modulator that generates a clock at the required rate inside the chip itself there by removing the need for off-chip analog PLLs. The packetized clock may include a packet interface that receives a flow credit packet that includes a plurality of flow credit counts, one flow credit count for each data flow, and forwards a flow credit count for each data flow to one of a plurality of clock generators to generate a new clock signal for each data flow.