Packetized Interface for Die-to-Die Interconnects
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Solution Overview
Problem
Current semiconductor integrated circuits face challenges in integrating diverse intellectual property blocks on a single die due to issues like power consumption, spacing, routing complexity, and lack of interoperability, particularly in multi-chip packages using PCIe interconnects.
Innovation Solution
A packetized interface is introduced for high-speed, low-power on-die or die-to-die interconnects within a package, allowing for fewer wires and scalable interconnects that tolerate interconnect delays, enabling efficient communication across multiple cycles and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PCIe interconnect or proprietary internal interconnects are used within multi-chip package, then die-to-die connectivity is achieved, but power consumption increases and routing complexity increases
Solution Approach 1:
The interconnect is segmented into separate transmit and receive paths with independent control, allowing selective activation of communication channels based on data flow requirements, thereby reducing unnecessary power consumption while maintaining connectivity reliability
Solution Approach 2:
The patent changes the operational parameters of the interconnect by implementing asynchronous packetized communication with variable packet sizes and dynamic credit-based flow control, optimizing power consumption based on actual data transmission needs rather than continuous operation
2Reliability
If PCIe interconnect or proprietary internal interconnects are used within multi-chip package, then die-to-die connectivity is achieved, but routing complexity increases
Solution Approach 1:
The packetized interface serves multiple functions including data transmission, flow control, error handling, and credit management through a unified protocol, reducing the need for separate dedicated routing mechanisms and simplifying overall system complexity
Solution Approach 2:
The patent introduces a packetization layer as an intermediary that translates between different interconnect protocols and the physical transmission medium, abstracting away routing complexity from the core logic blocks while ensuring reliable die-to-die connectivity
3Adaptability or versatility
If single chip system-on-chip solutions integrate processor cores, memory controller hub, and input/output controller, then functionality is combined, but integration difficulty increases due to IP block compatibility issues
Solution Approach 1:
The packetized interface protocol serves as a universal communication standard that can accommodate different IP blocks (processor cores, memory controllers, I/O controllers) from various vendors, enabling heterogeneous integration on a single chip without requiring proprietary interconnect designs for each block
Solution Approach 2:
The system is segmented into independent functional blocks that communicate through the standardized packetized interface, allowing each IP block to be designed and validated independently before integration, thereby reducing overall integration complexity while maintaining high functionality
4Use of energy by moving object
If packetized interface is used for on-die or die-to-die interconnects, then power consumption is reduced and routing congestion is relieved, but implementation complexity increases
Solution Approach 1:
The packetized interface implements self-service mechanisms including automatic credit-based flow control, error detection and correction, and packet retransmission logic within the interface itself, reducing the need for external control logic and minimizing implementation complexity despite the advanced communication protocol
Data Source
AI summary
In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an on-chip protocol and a packetization layer coupled to the fabric to receive command and data information from the fabric on multiple links and to packetize the information into a packet for transmission from the die to another die via an in-package packetized link. Other embodiments are described and claimed.