Serial Memory Interface Partitioning for Low-Latency Acknowledgements
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Solution Overview
Problem
Programmable integrated circuits face challenges in supporting multiple serial memory interface protocols and minimizing acknowledgement processing latency, particularly due to limited retransmission buffer sizes, which can reduce link performance.
Innovation Solution
A programmable integrated circuit with a memory interface that combines programmable logic and hardwired logic circuitry, featuring a soft memory controller for packet formation, a cyclic redundancy check checking circuit, and a retransmission buffer to manage sequence numbers and acknowledgments, allowing for efficient data packet processing across different memory protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a programmable integrated circuit uses a soft memory controller for packet formation logic, then adaptability to multiple memory protocols is improved, but acknowledgement processing latency increases
Solution Approach 1:
The memory interface is segmented into two distinct parts: a programmable logic portion implementing a soft memory controller for protocol adaptability, and a hardwired logic portion for time-critical functions such as sequence number extraction, acknowledgment generation, and cyclic redundancy check processing. This segmentation allows each part to be optimized for its specific function, resolving the contradiction between adaptability and latency.
2Device complexity
If the retransmission buffer size is limited, then device complexity is reduced, but link performance deteriorates in the presence of acknowledgement processing latency
Solution Approach 1:
The hardwired logic circuitry performs preliminary actions by pre-generating acknowledgment packets and pre-managing sequence numbers in advance, before the soft memory controller completes its protocol-specific processing. This allows the system to maintain high link performance with limited buffer sizes, as the time-critical acknowledgment functions are already prepared and do not wait for the programmable logic to complete its operations.
Data Source
AI summary
A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.