Semiconductor Package Pad Array With Ground Plate for Noise Reduction
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Solution Overview
Problem
Noise is generated in dense and highly integrated semiconductor packages due to inductance of wiring systems, affecting device performance.
Innovation Solution
A semiconductor package design that includes a pad array with a ground plate surrounding signal and power lines, and additional ground vias to reduce loop inductance, improving signal path reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wiring systems are used in dense and highly integrated semiconductor packages, then device density and integration are improved, but noise voltage is generated due to inductance
Solution Approach 1:
The ground connection is segmented into multiple ground vias distributed around the signal path, rather than using a single ground connection. This segmentation reduces the loop inductance by creating multiple parallel current paths to ground, thereby reducing noise voltage while maintaining high device density
Solution Approach 2:
The ground plate is designed to surround and enclose the signal lines and vias, creating a nested structure where the ground plate acts as an outer shell. This nested configuration minimizes the loop area and reduces inductance, allowing dense integration without excessive noise
2Reliability
If ground plate and additional ground vias are added to reduce loop inductance, then noise is reduced and signal integrity is improved, but device complexity increases
Solution Approach 1:
Multiple ground vias are merged into a unified ground plate structure that surrounds the signal path. This combining approach maintains the benefits of multiple ground connections (reduced inductance) while simplifying the overall structure compared to having separate, scattered ground elements throughout the package
Data Source
AI summary
A semiconductor package includes a package substrate and a first semiconductor device disposed on the package substrate, wherein the package substrate includes a pad array, wherein the pad array includes a first signal pad, a first power pad, and a second signal pad sequentially disposed adjacent to each other in a row, a first via spaced apart from the first signal pad, a second via spaced apart from the second signal pad, a first signal line which connects the first signal pad and the first via, a second signal line which connects the second signal pad and the second via, a ground plate disposed to surround the first via, the second via, the first signal line, and the second signal line, and a first ground via disposed between the first signal line and the second signal line, and connected to the ground plate.