Semiconductor Pad Barrier Stack With Phase-Tuned Diffusion Blocking
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Solution Overview
Problem
In semiconductor manufacturing, metal diffusion through barrier layers poses challenges in maintaining the integrity and performance of interconnect structures, leading to potential failures in electrical connections.
Innovation Solution
A multi-layer barrier structure comprising nano-crystalline, amorphous, and poly-crystalline phases is formed to prevent metal elements from diffusing through, with each layer having specific thickness and nitrogen concentration profiles to misalign threading dislocation defects, thereby enhancing the barrier's effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single barrier layer is used to prevent metal diffusion, then the structure is simple, but metal diffusion occurs through threading dislocation defects reducing reliability
Solution Approach 1:
The barrier layer is segmented into multiple distinct layers (first barrier layer, second barrier layer, third barrier layer) with different crystal phases and compositions. Each layer targets specific diffusion pathways, with the first layer blocking grain boundary diffusion, the second layer blocking threading dislocation defects, and the third layer providing additional protection, collectively achieving superior diffusion prevention compared to a single barrier layer
Solution Approach 2:
The barrier structure employs composite materials with different crystal phases (nanocrystalline, amorphous, polycrystalline) and compositions (tungsten nitride, tantalum nitride, titanium nitride) arranged in specific sequences. This composite approach leverages the unique properties of each material phase to address different diffusion mechanisms, creating a multi-functional barrier system that simultaneously prevents various metal diffusion pathways
2Reliability
If barrier layer thickness is increased to block metal diffusion, then diffusion prevention improves, but manufacturing precision requirements increase due to threading dislocation defects
Solution Approach 1:
Each barrier layer is designed with specific local qualities tailored to its function: the first barrier layer has nanocrystalline structure with specific grain size for blocking grain boundary diffusion, the second barrier layer has amorphous structure with specific thickness range (50-150 nm) optimized for blocking threading dislocation defects, and the third barrier layer has polycrystalline structure for additional protection. This localized optimization of properties in each layer achieves superior diffusion prevention without requiring excessive thickness in any single layer
Solution Approach 2:
The invention changes multiple parameters of the barrier layers including crystal phase (nanocrystalline, amorphous, polycrystalline), composition (different metal nitrides), thickness (varying across layers), and nitrogen concentration profiles. By optimizing these parameters in combination across multiple layers, the system achieves effective diffusion prevention while maintaining manufacturable thickness ranges that do not impose excessive precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the failure rate of semiconductor structures by effectively blocking metal diffusion to the pad layer, ensuring reliable electrical performance with a failure rate lower than 1%.
Implementation Method 1
A barrier layer is formed above the conductive line and below the pad layer. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a poly-crystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase.
Data Source
AI summary
A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.