On-Die Pad Capacitance Test Circuit for PVT Variation Screening
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Solution Overview
Problem
Current methods for testing pad capacitance in electronic circuits are limited, as they require the circuit to be turned off, are time-consuming, and only measure under specific process, voltage, and temperature (PVT) conditions, leading to incomplete and error-prone data due to package trace interference.
Innovation Solution
A pad capacitance test circuit is integrated on the silicon die to measure capacitance across multiple PVT conditions, allowing for accurate and efficient testing of pad capacitance without package trace errors, using a method that couples a pad to a supply voltage through a pullup resistor and measures the final voltage to determine capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If TDR method is used to measure pad capacitance, then measurement can be performed, but the circuit must be turned off and only one PVT condition can be measured
Solution Approach 1:
The patent changes the measurement parameters by performing capacitance measurements at multiple PVT corners (process, voltage, and temperature conditions) rather than a single condition. This allows the measurement system to adapt to different operating conditions and provide comprehensive capacitance data across the full operating range of the device.
Solution Approach 2:
The measurement system is designed to universally measure pad capacitance across multiple PVT conditions, making it adaptable to various operating scenarios. The system can function under different process variations, voltage levels, and temperature ranges, providing comprehensive characterization of the pad capacitance behavior.
2Measurement precision
If TDR method is used, then pad capacitance can be measured, but the process is time consuming and only a few units can be tested
Solution Approach 1:
The patent replaces the external TDR measurement system with an integrated on-die measurement circuit. This substitution eliminates the need for time-consuming external probing and allows for rapid automated measurements to be performed directly on the silicon die, significantly increasing testing throughput and productivity.
Solution Approach 2:
The measurement circuit is pre-integrated on the die during manufacturing, allowing capacitance measurements to be performed immediately without requiring external setup or calibration. This preliminary integration enables rapid high-volume testing to be conducted as part of the standard manufacturing process.
3Quantity of substance
If measurement is performed at pin level, then data can be collected, but package traces introduce additional error
Solution Approach 1:
The patent extracts the measurement function from the external pin level and relocates it directly to the pad level on the die. By taking out the measurement capability from the external testing environment and integrating it on-chip, the system eliminates the influence of package traces and external interconnects that would otherwise introduce measurement errors.
Solution Approach 2:
The on-die measurement circuit acts as an intermediary between the pad and the measurement function. Instead of measuring from the external pin through package traces, the intermediary measurement circuit directly accesses the pad capacitance on the die, providing accurate measurements free from package trace interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate and high-volume testing of electronic circuits, allowing for screening and collection of variation data across units, while the circuit is powered on, reducing errors and providing comprehensive PVT corner data.
Implementation Method 1
couple a first pad to a supply voltage through a pullup resistor
Implementation Method 2
measure a first voltage of the first pad at a first time point at or near the end of the time period to enable a capacitance of the first pad to be determined
Data Source
AI summary
A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor.