Pad ESD Spreading via PMOS Pre-Charge
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Solution Overview
Problem
Integrated circuits face increased sensitivity to electrostatic discharge (ESD) due to decreasing power supply voltage levels and increasing component density, making it challenging to design effective ESD protection circuits that maintain compatibility with older ICs while ensuring noise immunity and not increasing silicon area.
Innovation Solution
The implementation of output PMOS devices in the output buffer of I/O pads, which charge pad capacitance during an ESD event to distribute energy and reduce peak voltage, combined with a clamp control circuit that activates a clamp device and enables PMOS devices while disabling NMOS devices to share ESD energy across all pads, thereby reducing maximum voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If power supply voltage levels are decreased to increase IC density and operating speed, then IC operating speed and density are improved, but sensitivity to ESD effects increases
Solution Approach 1:
The pad capacitance is pre-charged to a high voltage level (e.g., VDDIO or higher) before an ESD event occurs. This preliminary charging of the capacitance through the PMOS device during normal operation ensures that when ESD strikes, the pre-stored energy in the capacitance immediately counteracts the ESD voltage spike, reducing the peak voltage experienced by the IC core.
Solution Approach 2:
The invention dynamically changes the voltage parameter of the pad capacitance. During normal operation, the capacitance is maintained at a high voltage level through the PMOS device. When ESD occurs, this voltage parameter change (from pre-charged high voltage to discharged state) creates a counter-voltage that opposes the ESD pulse, effectively reducing ESD sensitivity without requiring higher supply voltages for normal operation.
2Reliability
If ESD protection circuits are designed to meet high performance requirements and tolerate voltages above FET tolerance, then ESD robustness is improved, but noise immunity deteriorates
Solution Approach 1:
The protection mechanism is dynamic rather than static. The PMOS device and pad capacitance are actively controlled to provide protection only when needed. The control circuit monitors pad voltage and activates the PMOS device and capacitance charging when ESD conditions are detected, while keeping the protection mechanism inactive during normal operation to maintain noise immunity.
Solution Approach 2:
The pad capacitance serves dual purposes: it provides normal pad functionality during regular operation and automatically provides ESD protection when needed. The capacitance charges itself through the PMOS device during normal operation and automatically discharges to counteract ESD pulses, making the system self-protecting without requiring external intervention or compromising noise immunity.
3Reliability
If ESD protection circuits are designed to meet high performance requirements, then ESD robustness is improved, but silicon area increases
Solution Approach 1:
The pad capacitance and PMOS device are designed to serve multiple functions: normal pad operation during regular functioning and ESD protection during voltage spikes. By making these components multi-functional, the invention avoids adding dedicated separate protection circuitry, thereby achieving improved ESD robustness without proportionally increasing silicon area.
Solution Approach 2:
The invention merges the ESD protection function with the existing pad structure by integrating the PMOS device and pad capacitance into the normal pad circuitry. This consolidation allows the same hardware components to provide both standard pad functionality and ESD protection, eliminating the need for separate protection circuits and reducing overall silicon area consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances ESD performance by reducing peak voltage and improving reliability, allowing for better compatibility with higher voltage requirements and maintaining noise immunity without increasing silicon area.
Implementation Method 1
charge a pad capacitance (which, in some cases, may be approximately 3 pF) corresponding to the physical pad or pad cell, to spread out the energy generated by the ESD event
Data Source
AI summary
A system, e.g. an integrated circuit or part, may include a plurality of pads, e.g. digital I/O pads, each comprising a physical pad and associated pad circuit. In case of an ESD event affecting one or more of the digital I/O pads, PMOS devices configured in an output buffer section between an I/O pad supply rail and the physical output pad—within their respective pad circuits in the affected digital I/O pads—may all be turned on in response to the ESD event. This may allow the capacitance of each pad, in some cases approximately 3 pF capacitance per pad, to charge up, absorbing the energy of the ESD event and reducing the peak voltage the integrated circuit or part experiences as a result of the ESD event. The reduced peak voltage may be directly correlated with improved ESD performance of the product.