Integrated Fault Detection Logic in Semiconductor Pads
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Solution Overview
Problem
Existing techniques for detecting faults in electrical interconnection devices, such as pads in semiconductor integrated circuits, do not provide sufficient 'coverage' and fail to reliably detect certain types of faults, particularly 'stuck at' 0 or 1 faults, due to limitations in the use of X-OR gate trees and decoupling buffers.
Innovation Solution
An interconnection device with an integrated fault detecting logic module comprising a combinatorial network of gates, including X-OR gates, that is directly connected to the outputs of internal devices within the pad, enabling improved detection of faults by providing a detecting signal indicative of test results, thereby enhancing fault coverage without increasing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If X-OR gate trees with decoupling buffers are used for fault detection, then the circuit structure is established, but the fault detection coverage is insufficient and cannot reliably detect stuck-at faults
Solution Approach 1:
The invention extracts the fault detection function from the traditional external test setup and integrates it directly into the pad structure itself. By taking out the detection logic from the test equipment and embedding it within the pad, the system achieves continuous monitoring capability without adding external complexity, thereby improving reliability while maintaining manageable device complexity
Solution Approach 2:
The pad structure is designed to perform multiple functions: normal signal transmission and integrated fault detection. The detection module within the pad can monitor both digital and analog signals, detect stuck-at faults, and provide detection outputs that can be used by external test equipment. This multi-functionality improves fault detection coverage without requiring separate dedicated detection circuits, thus avoiding increased device complexity
2Reliability
If decoupling buffers are inserted between pad pins and logic circuit, then signal isolation is achieved, but fault detection capability is lost for buffers following the X-OR gate connection point
Solution Approach 1:
The invention implements preliminary fault detection by placing detection logic at strategic points within the pad structure, before signals proceed through decoupling buffers to the logic circuit. This preliminary detection capability allows faults to be identified early in the signal path, maintaining detection capability even when buffers are present, thereby improving reliability without compromising ease of operation
Solution Approach 2:
The detection module acts as an intermediary between the pad pin and the logic circuit, providing fault detection information without interfering with the normal signal flow through decoupling buffers. This intermediary detection mechanism maintains both fault detection capability and ease of operation by providing accessible detection outputs while allowing the buffer isolation function to remain intact
3Reliability
If traditional pad structure without integrated detection is used, then device complexity is low, but fault detection coverage and reliability are insufficient
Solution Approach 1:
The invention merges the fault detection function with the pad structure by integrating detection logic directly into the pad. This combination allows the pad to simultaneously perform its normal function of signal transmission and the additional function of fault detection, thereby improving reliability while minimizing the increase in device complexity through functional integration rather than addition of separate components
Data Source
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AI summary
An electrical interconnection integrated device is described, comprising: a plurality of electrical terminals (16-26) connectable to an integrated electronic circuit (400) on a chip common to said interconnection device; at least an inside electrical device (43;33;34) provided with a respective input connected to a first terminal (18;24;25) of said plurality and a respective output (57;62;63); a fault detecting logic module (50) having a first input (57;62;63) connected to said output of the inner electrical device (43;33;34) and provided with a detecting terminal for supplying a fault detecting signal (ipp_xor).