Pad Formation in 3D Stacked Wafer Without Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for forming pads in wafers with three-dimensional stacking structures require separate etching of Si substrates, which can damage super contacts and lead to imaging issues and dishing during dielectric layer planarization, making subsequent processes difficult.
Innovation Solution
A method that omits the separate etching of Si substrates by bonding a device wafer and a handling wafer, thinning the back side of the device wafer, forming an anti-reflective layer and PMD dielectric layer, creating vias on the back sides of super contacts, and forming a pad on these vias, allowing for pad formation without damaging the substrate or super contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a separate etching process is performed on the Si substrate after back side thinning, then the pad formation can proceed, but the super contacts and Si substrate surface are likely to be damaged
Solution Approach 1:
The patent extracts and removes the harmful separate etching step from the process flow. Instead of performing a separate etching process on the Si substrate that damages super contacts, the method directly forms vias through the dielectric layers to reach the super contacts, thereby achieving pad formation without the damaging etching operation.
Solution Approach 2:
The patent inverts the conventional approach by not etching the Si substrate at all. Rather than removing material from the substrate to create access to super contacts, the method deposits dielectric layers and forms vias through them, reversing the traditional etching-first approach to a deposition-and-via-formation approach that preserves substrate integrity.
2Ease of manufacture
If the Si substrate thickness is reduced through separate etching, then pad formation becomes possible, but imaging characteristics of the image sensor deteriorate
Solution Approach 1:
The patent extracts the harmful separate etching step that reduces substrate thickness. By removing this etching operation entirely and replacing it with dielectric layer deposition and via formation, the method maintains the original substrate thickness and preserves the imaging characteristics of the image sensor while still enabling pad formation.
3Ease of manufacture
If dielectric layer planarization is performed through CMP, then the pad can be formed, but dishing occurs making subsequent processes difficult
Solution Approach 1:
The patent extracts and eliminates the CMP planarization step from the process. Instead of performing chemical mechanical polishing that causes dishing, the method directly forms vias through the dielectric layers and proceeds to pad formation, removing the source of dishing and the associated complexity of target setting and isolation requirements.
4Manufacturing precision
If target setting for dielectric layer planarization is required, then the Si substrate and pad must be isolated from each other
Solution Approach 1:
The patent extracts and removes the entire planarization process step that requires target setting and isolation. By eliminating CMP and directly forming vias through the dielectric layers, the method removes the need for complex target setting procedures and isolation requirements, simplifying the overall manufacturing process.
Data Source
AI summary
A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.