Pad Invariant FPGA to ASIC Migration via Programmable Logic Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing design and fabrication of custom or semi-custom integrated circuits (ICs) are time-consuming and expensive, with high Non-Recurring Engineering (NRE) costs, and there is no convenient migration path from Field Programmable Gate Arrays (FPGAs) to Application Specific Integrated Circuits (ASICs), leading to inefficiencies in design cycles and silicon real estate usage.
Innovation Solution
A three-dimensional semiconductor device with a first module layer containing circuit blocks and a second module layer positioned above or below, featuring a memory array to program programmable logic circuits, allowing for conversion from FPGA to ASIC without altering pad structures or I/O characteristics, using memory elements like fuses, SRAM cells, or EPROMs to configure logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If custom or semi-custom ICs are used, then manufacturing precision and reliability are improved, but design time and NRE costs increase significantly
Solution Approach 1:
The patent implements a programmable logic array (PLA) that can be configured after fabrication to perform different logic functions. This dynamic reconfigurability allows the same physical device to adapt to different application requirements, eliminating the need for lengthy redesign cycles when bugs are found or requirements change, thus reducing design time while maintaining reliability.
Solution Approach 2:
The patent uses programmable memory elements (such as EEPROM or FLASH) to store configuration data that defines the logic functions of the PLA. By changing the programming parameters of these memory elements, the device can be reconfigured for different applications without physical modification, significantly reducing both design cycle time and NRE costs while maintaining the reliability of custom ICs.
2Adaptability or versatility
If FPGAs are used, then design flexibility and time-to-market are improved, but silicon area consumption increases
Solution Approach 1:
The patent segments the logic implementation into fixed interconnect structures and programmable logic elements. The interconnect framework provides the routing infrastructure, while programmable PLA elements implement specific logic functions. This segmentation allows efficient use of silicon area by only programming the necessary logic elements rather than providing full programmability throughout the device, reducing area consumption while maintaining design flexibility.
Solution Approach 2:
The patent creates a universal platform where a single FPGA device can implement multiple different logic functions through programmable PLA elements. The same physical device serves as different custom ICs for different applications, eliminating the need for multiple dedicated ASIC designs. This multi-functionality reduces silicon area consumption compared to having separate custom ICs for each application while maintaining full design flexibility.
3Ease of manufacture
If FPGAs are used, then ease of manufacture and design iteration are improved, but pad structure complexity and I/O resource consumption increase
Solution Approach 1:
The patent extracts the configuration data storage function into separate programmable memory elements (EEPROM/FLASH) that are distinct from the core PLA logic structures. This separation allows the pad structures to remain simple and dedicated to their I/O functions, while the complex configuration management is handled by the memory elements. The result is reduced pad structure complexity and more efficient I/O resource utilization while maintaining ease of manufacture and design iteration capabilities.
Data Source
AI summary
A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having predetermined positions within the device; and a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabricating methods without altering the predetermined positions of the pads and the circuit blocks.