Pad Electrode Layout Shift to Contain Passivation Layer Cracks
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Solution Overview
Problem
The reliability of passivation layers covering pad electrodes in semiconductor devices is a challenge, particularly in three-dimensional integrated circuits, as cracks can form in the passivation layer due to the formation of long valleys between pad electrodes, which can compromise the integrity of the semiconductor device.
Innovation Solution
The pad electrodes are arranged with a deliberate shift relative to the underlying topmost wiring patterns, ensuring that any cracks in the passivation layer are contained above the wiring patterns, preventing them from reaching the underlying circuitry by forming a pattern shift during the lithography process without requiring new photomasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pad electrodes are arranged in a regular grid pattern aligned with wiring patterns, then manufacturing process is simple and straightforward, but cracks can form in the passivation layer and reach the underlying circuitry
Solution Approach 1:
The pad electrodes are deliberately arranged in an asymmetric pattern that is offset from the underlying wiring patterns. This asymmetric arrangement ensures that cracks forming in the passivation layer between pad electrodes do not align with and reach the underlying wiring patterns, thereby preventing circuit damage while maintaining manufacturing feasibility through standard lithography processes.
2Reliability
If photomasks are redesigned to account for crack propagation paths, then passivation layer reliability can be improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The asymmetric arrangement of pad electrodes is predetermined in the design stage to proactively prevent crack propagation to underlying circuitry. This preliminary design action eliminates the need for complex photomask modifications or additional manufacturing steps, as the crack prevention is achieved through the inherent geometric arrangement rather than through complex masking processes.
Data Source
AI summary
In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.