Pad Redistribution Chip for Compact Stacked Packages
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Solution Overview
Problem
Conventional stacked semiconductor packages become bulky due to wires extending in horizontal or vertical directions to avoid interference, contradicting the trend towards compactness.
Innovation Solution
A pad redistribution chip design with center and edge pads on a wafer, connected by traces, and a method for manufacturing this chip, including insulation and metal layer formation, with anisotropic dielectric films and flexible PCBs for compact stacked packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wires are extended in horizontal or vertical direction to avoid interference, then wire interference is avoided, but package size increases
Solution Approach 1:
The patent transitions from planar wire routing (2D horizontal/vertical extension) to three-dimensional vertical stacking with through-silicon vias (TSVs). Electrical connections are established by routing signals vertically through the substrate via TSVs, then redistributing them on the opposite surface. This dimensional change eliminates wire interference while maintaining compact package footprint.
Solution Approach 2:
The patent introduces through-silicon vias (TSVs) as intermediary structures to transfer electrical signals between different layers. The TSVs act as vertical conduits that penetrate the substrate, enabling compact inter-layer connections without requiring long horizontal wire traces, thus resolving the contradiction between reliable connections and compact size.
2Productivity
If more semiconductor chips are stacked to increase mounting efficiency, then mounting efficiency per unit volume increases, but wire interference increases
Solution Approach 1:
The patent enables multi-chip stacking by implementing vertical signal routing through TSVs. Each chip layer can be independently connected to the substrate below through vertical vias, eliminating the need for horizontal wire routing between stacked chips. This allows higher chip density without increasing wire interference.
Solution Approach 2:
The patent segments the electrical connection paths into vertical TSV routes and horizontal redistribution layers. By separating the vertical signal transmission function (handled by TSVs) from the horizontal signal routing function (handled by redistribution traces on chip surfaces), the design enables compact multi-chip stacking while avoiding wire interference.
3Volume of stationary object
If center pads are redistributed to edge pads through traces, then package compactness is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent performs pad redistribution during the wafer fabrication stage using standard semiconductor manufacturing processes. The TSVs and redistribution traces are formed as part of the wafer-level processing before chip dicing, which simplifies subsequent assembly. This preliminary action embeds the redistribution functionality directly into the chip structure, avoiding complex post-assembly modifications.
Solution Approach 2:
The patent uses standard semiconductor fabrication techniques (photolithography, etching, deposition, plating) to create the pad redistribution structure. These are universal, well-established processes that can be integrated into existing manufacturing lines, reducing the need for specialized equipment or complex manufacturing steps despite the added functionality.
Data Source
AI summary
A substrate includes a substrate; a number of pad redistribution chips stacked on the substrate and on one another after being rotated 90° in a predetermined direction relative to one another, the pad redistribution chips having a number of center pads positioned at the center thereof, a number of (+) edge pads positioned on an end thereof while corresponding to those of the center pads lying in (+) direction from a middle center pad located in the middle of the center pads, a number of (−) edge pads positioned on the other end thereof while corresponding to those of the center pads lying in (−) direction with symmetry to those of the center pads lying in the (+) direction, and a number of traces for electrically connecting the center pads to the corresponding (±) edge pads, respectively; a flexible PCB for electrically connecting the substrate to the pad redistribution chips; and an anisotropic dielectric film for electrically connecting the pad redistribution chips to the flexible PCB and the substrate to the flexible PCB.


