Pad-on-Solder-Mask Package for Surface Signal Breakout
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Solution Overview
Problem
Conventional semiconductor package designs require additional layers for signal breakout, leading to increased size, cost, and potential performance reduction, as well as manufacturability and reliability issues due to the need for sub-layer trace routing and underfill requirements.
Innovation Solution
The implementation of a Pad on Solder Mask (PoSM) semiconductor substrate package design, which allows for selective reduction of First Level Interconnect (FLI) pads and the use of nickel pads within the solder resist layer to enable surface escape of signals at a single top layer, eliminating the need for sub-layer trace routing and reducing the overall package thickness and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional package designs use additional substrate layers for signal breakout, then signal routing capability is improved, but package thickness and manufacturing cost increase
Solution Approach 1:
The patent moves signal breakout from the substrate plane to the package surface plane by implementing pads on the solder mask layer. This dimensional shift allows signals to escape at the top surface rather than requiring additional substrate layers, effectively resolving the contradiction between routing capability and package thickness.
Solution Approach 2:
The invention extracts the signal breakout function from the substrate structure and relocates it to the solder mask layer. By taking out the routing capability requirement from the substrate, the design eliminates the need for additional substrate layers while maintaining full signal routing functionality.
2Reliability
If conventional designs require sub-layer trace routing, then signal connectivity is achieved, but manufacturing complexity and reliability issues increase
Solution Approach 1:
The patent extracts the trace routing function from the substrate and implements it directly on the solder mask layer through printed conductive traces. This eliminates the complexity of sub-layer routing and associated manufacturing issues while maintaining reliable signal connectivity.
Solution Approach 2:
The invention changes the structural parameter of the package from multi-layer substrate construction to a simplified single-layer substrate with surface-mounted routing. This parameter change reduces manufacturing complexity and eliminates reliability issues associated with sub-layer trace routing and underfill requirements.
3Quantity of substance
If FLI pads are reduced in size for higher density, then package density is improved, but pad functionality and signal integrity may be compromised
Solution Approach 1:
The patent relocates pads from the substrate layer to the solder mask surface layer, creating a vertical separation between the compact substrate and the functional pads. This allows the substrate to maintain high density while pads retain sufficient size for reliable functionality and signal integrity.
Solution Approach 2:
The invention segments the package structure into distinct functional layers: the substrate layer for high-density interconnects and the solder mask layer for larger, more reliable pads. This segmentation allows each layer to be optimized independently, achieving both high density and reliable pad functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in a thinner, cost-effective, and potentially more performant 4L semiconductor package with increased density and reliability, as it allows for greater signal breakout density and eliminates the need for additional substrate layers, thereby reducing complexity and manufacturing costs.
Implementation Method 1
each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls
Implementation Method 2
a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfacing the functional silicon die to a substrate through the plurality of solder balls at a top surface of the solder resist layer
Data Source
AI summary
In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.