Multi-Layer Pad Structure for Uniform Soldering Heights

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Solution Overview

Problem

In existing wiring substrates, non-uniform via-hole diameters lead to inconsistent pad heights, affecting connection reliability between semiconductor chips and pads, resulting in open or short defects during soldering due to inadequate or excessive solder distribution.

Innovation Solution

The wiring substrate design includes pad structures with via-wirings of different diameters, featuring a first metal layer on the insulating layer and inner via-hole walls, a second metal layer filling the via-holes and extending beyond the insulating layer with a flat upper surface, and a third metal layer on top, ensuring consistent pad heights and solder distribution by maintaining a constant distance from the insulating layer to the second metal layer's surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If electrolytic plating is performed to form pad structures with via-wirings, then electrical connection between wiring layers is achieved, but non-uniform via-hole diameters cause inconsistent pad heights leading to connection reliability issues

Engineering Contradiction:
Improveconnection reliabilityVSAvoidpad height uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The pad structure is divided into three distinct metal layers: a first metal layer forming the via-wiring inside the via-hole, a second metal layer forming a planarized upper surface, and a third metal layer forming the final pad structure. This segmentation allows each layer to serve a specific function - the first layer provides electrical connection, the second layer ensures uniform height, and the third layer provides the bonding surface, thereby resolving the contradiction between achieving electrical connection and maintaining pad height uniformity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a single-layer pad structure to a multi-layer vertical structure. By adding the second metal layer that extends beyond the via-hole and provides a planarized upper surface, the solution moves the uniformity control to a new dimensional level (the upper surface plane), allowing via-wirings of different diameters to all reach the same height reference plane, thus ensuring consistent pad heights despite variations in via-hole dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If pad heights are inconsistent due to varying via-hole diameters, then manufacturing process is simplified, but soldering defects (open or short) occur due to inadequate or excessive solder distribution

Engineering Contradiction:
Improvepad structure formationVSAvoidsoldering quality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The second metal layer is formed in advance to create a planarized upper surface before the final pad structure is completed. This preliminary planarization action ensures that all via-wirings, regardless of their diameter variations, reach the same reference plane, thereby preventing soldering defects caused by height inconsistencies while maintaining ease of manufacture through a systematic multi-layer formation process.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances connection reliability by maintaining consistent intervals between pads and semiconductor chip electrodes, reducing open and short defects by ensuring adequate solder distribution and uniform pad heights across different via-wiring diameters.

Implementation Method 1

an electrolytic plated layer is formed on the seed layer exposed in the opening portions of the resist pattern by an electrolytic plating method of feeding power from the seed layer

Methodology Applied
Scientific EffectElectrolytic plating: Electroplating

Data Source

PatentUS11594478B2Wiring substrate, semiconductor package and method of manufacturing wiring substrate
Publication Date: 2023.02.28 SHINKO ELECTRIC IND CO LTD
  • US11594478B2 patent drawing
  • US11594478B2 patent drawing
  • US11594478B2 patent drawing

AI summary

A second wiring layer is connected to a first wiring layer via an insulating layer. The second wiring layer comprises pad structures. Each pad structure includes a first metal layer formed on the insulating layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The pad structures comprises a first pad structure and a second pad structure. A via-wiring diameter of the first pad structure is different from a via-wiring diameter of the second pad structure. A distance from an upper surface of the insulating layer to an upper surface of the second metal layer of the first pad structure is the same as a distance from the upper surface of the insulating layer to an upper surface of the second metal layer of the second pad structure.