Pad Tracking Bias Circuit for Leakage Path Blocking
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Solution Overview
Problem
Current chip designs with pad tracking face increased power consumption due to the need for multiple bias circuits, which is inefficient and not effectively managed, especially when system power is on but the chip's power is off, leading to leakage paths.
Innovation Solution
An external bias circuit powered by an additional power source or an electrostatic discharging bus is introduced, which generates a bias signal to block leakage paths within the I/O buffer, allowing the pad to be coupled to an electrostatic discharging bus through a diode, and shared among multiple pads, reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pad-tracking design is implemented to block leakage paths, then reliability is improved, but power consumption increases with the number of pads
Solution Approach 1:
The patent merges multiple separate bias circuits into a single shared bias circuit that serves multiple I/O buffers and pads simultaneously. This consolidation maintains the leakage-blocking function across all pads while significantly reducing the total power consumption by eliminating redundant circuitry.
Solution Approach 2:
The shared bias circuit is designed to provide bias signals to multiple I/O buffers through a universal structure. This multi-functional approach allows one bias circuit to perform the work of what would traditionally require multiple separate bias circuits, reducing overall power consumption while maintaining reliability across all pads.
2Reliability
If separate bias circuits are provided for each I/O buffer, then each pad can independently block leakage paths, but device complexity increases
Solution Approach 1:
The patent combines multiple independent bias circuits into a single shared bias circuit structure. This merging reduces device complexity by eliminating redundant components while maintaining the ability to block leakage paths across all pads through the unified bias signal distribution network.
Solution Approach 2:
The shared bias circuit is segmented into multiple output branches that can independently control different I/O buffers. This segmentation allows the single bias circuit to function as multiple separate circuits would, maintaining independent leakage blocking capability for each pad without requiring separate physical bias circuits.
Data Source
AI summary
A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.