Pad-Tracking Output Buffer for Leakage-Free GPIO Mode Switching
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Solution Overview
Problem
Conventional GPIO designs experience leakage current during power ramp up and ramp down when switching between input and fail-safe modes due to the output buffer's enablement and disablement.
Innovation Solution
An output buffer design incorporating a first transistor, a second transistor, and a pad-tracking circuit, where the pad-tracking circuit generates a gate control signal to manage the transistors' states based on the pad voltage, ensuring no leakage current by disabling the transistors appropriately during power transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the output buffer is enabled/disabled during mode switching, then the GPIO can operate between input mode and fail-safe mode, but leakage current occurs during power ramp up and ramp down
Solution Approach 1:
The pad-tracking circuit generates the gate control signal for the first transistor in advance during power ramp up or ramp down, before the supply voltage reaches its final level. This preliminary action ensures the transistor is properly controlled during the transition, preventing leakage current while maintaining mode switching capability
Solution Approach 2:
The pad-tracking circuit acts as an intermediary between the control circuit and the first transistor. It generates the gate control signal based on the pad voltage, mediating the control of the transistor during power transitions to prevent leakage while enabling mode switching
Data Source
AI summary
The present invention provides an output buffer including a first transistor, a second transistor and a pad-tracking circuit is disclosed. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad-tracking circuit is coupled to the control circuit and the first transistor, and is configured to generate a gate control signal to a gate electrode of the first transistor. The output buffer is selectively operated in an input mode and a fail-safe mode, and when the output buffer switches between the input mode and the fail-safe mode and the supply voltage of the first transistor ramps up or ramps down, the pad-tracking circuit generates the gate control signal to the gate electrode of the first transistor according to the voltage of the pad.