Pad-Tracking Output Buffer for High-Voltage Input Tolerance
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Solution Overview
Problem
Conventional GPIO designs face stability and reliability issues due to weak voltage endurance of transistors, particularly when input signals with large swings exceed the supply voltage, risking damage to low-side transistors.
Innovation Solution
A pad-tracking mechanism is employed to control the output buffer, generating control signals to fully turn off P-type transistors and utilize N-type transistors as voltage dividers to manage gate-drain voltages, preventing supply voltage charging and ensuring high-voltage input tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional GPIO designs use transistors in output and input buffers to handle large input signal swings, then the circuit can process high-voltage inputs, but the transistors may be damaged due to high gate-drain voltages when voltage endurance is weak
Solution Approach 1:
The patent implements dynamic control of transistor operation modes through a pad-tracking mechanism. The output buffer transitions between push-pull mode (for normal operation) and triode mode (for high-voltage protection) based on real-time pad voltage detection. This dynamic adaptation allows the circuit to handle high-voltage inputs while protecting transistors from damage by adjusting their operating state according to voltage conditions
Solution Approach 2:
The patent introduces a pad voltage detector and control logic as intermediary components between the pad and the output buffer transistors. These intermediaries monitor pad voltage and generate appropriate control signals to switch transistor modes, acting as a protective layer that prevents direct exposure of transistors to damaging high voltages while maintaining signal integrity
2Adaptability or versatility
If the supply voltage is charged by high voltage from the pad, then the output buffer can handle large signal swings, but low-side transistors may be damaged due to high gate-drain voltages
Solution Approach 1:
The patent applies preliminary protective action by detecting pad voltage before it can cause damage to low-side transistors. The pad voltage detector continuously monitors the pad and triggers a mode switch to triode configuration before damaging gate-drain voltages can develop across the transistors. This preemptive measure prevents the harmful voltage stress from occurring in the first place
Solution Approach 2:
The output buffer dynamically switches between push-pull and triode modes based on real-time voltage conditions. When high voltage is detected on the pad, the control logic transitions the output buffer to triode mode, where all transistors operate in the linear region, naturally limiting gate-drain voltage differences and protecting against damage while still allowing high-voltage signal passage
3Productivity
If advanced semiconductor processes are used to improve manufacturing efficiency, then production cost decreases, but voltage endurance of transistors becomes weaker
Solution Approach 1:
The patent changes the operational parameters of the transistors rather than their physical structure. By controlling transistors to operate in triode mode during high-voltage conditions, the effective voltage stress parameters are reduced, allowing advanced process transistors with weaker inherent voltage endurance to safely handle high-voltage signals. This parameter control approach enables compatibility with modern low-voltage manufacturing processes
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AI summary
The present invention provides a circuit including an output buffer, a tracking circuit and a pre-driver, where the output buffer includes at least one P-type transistor and at least one N-type transistor, the at least one P-type transistor is coupled between a supply voltage and a pad, and the at least one N-type transistor is coupled between a ground voltage and the pad. In the operations of the circuit, the tracking circuit is configured to generate a tracking signal control signal according to a voltage level at the pad, and the pre-driver is configured to generate a control signal to control the at least one P-type transistor or the at least one N-type transistor according to the tracking signal.