Pad Wiring Eaves Coating for Ion Migration and Stress Control

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Solution Overview

Problem

Existing semiconductor devices face issues with ion migration in the peripheral region of pad wiring layers and stress on the pad wiring layers, which can affect device performance and reliability.

Innovation Solution

A semiconductor device design featuring a pad wiring layer with a first conductive layer and a second conductive layer having an eaves portion, along with a coating insulating film that exposes the upper surface of the insulating layer and covers the end surface of the first conductive layer, to suppress ion migration and reduce stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the pad wiring layer is fully covered with insulating film, then ion migration is suppressed, but stress on the pad wiring layer increases

Engineering Contradiction:
Improveion migration suppressionVSAvoidstress on pad wiring layer
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The insulating film is selectively formed only in the peripheral region of the pad wiring layer, not covering the entire surface. This local application suppresses ion migration at the edges where it occurs most frequently, while leaving the central bonding area uncovered to reduce stress concentration and allow thermal expansion, thereby resolving the contradiction between ion migration suppression and stress reduction

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If the insulating layer is fully covered, then manufacturing simplicity is maintained, but ion migration occurs in peripheral regions

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidion migration suppression
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The coating insulating film is applied selectively to the peripheral region of the pad wiring layer using a dip-coating or spray-coating method, which naturally deposits material only on exposed surfaces. This approach achieves ion migration suppression at critical edges without requiring complex full-coverage patterning processes, thus maintaining manufacturing simplicity while improving reliability

Inventive Principle:
Principle #3Local quality

3Stress or pressure

If the pad wiring layer is exposed in peripheral region, then stress is reduced, but ion migration is suppressed less effectively

Engineering Contradiction:
Improvestress on pad wiring layerVSAvoidion migration suppression
Core Design Contradiction:
Stress or pressureVSReliability

Solution Approach 1:

The coating insulating film is precisely positioned only in the peripheral region where ion migration occurs, leaving the central bonding area exposed for stress relief. This localized protection strategy targets the specific problem area (peripheral edges) without compromising the overall structural integrity or bonding performance, achieving both stress reduction and effective ion migration suppression

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260018547A1Semiconductor device and method of manufacturing the semiconductor device
Publication Date: 2026.01.15 ROHM CO LTD
  • US20260018547A1 patent drawing
  • US20260018547A1 patent drawing
  • US20260018547A1 patent drawing

AI summary

A semiconductor device, including: a semiconductor chip having an element forming surface; an insulating layer formed on the element forming surface of the semiconductor chip; a barrier conductive layer formed on the insulating layer; a pad wiring layer including a plurality of conductive layers, one of the plurality of conductive layers including an eaves portion protruding to an outward direction; a bonding member that is bonded to the pad wiring layer and supplies electric power to an element of the element forming surface; and a coating insulating film that is selectively formed on the insulating layer below the eaves portion, exposes an upper surface of the insulating layer to a peripheral region of the pad wiring layer, and coats both an upper surface and a side surface of an end portion of the barrier conductive layer.