Padless Semiconductor Conductive Lines for Peripheral Circuit Area Reduction
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Solution Overview
Problem
Conventional semiconductor device fabrication techniques face challenges with insufficient patterning margin and critical dimension uniformity due to the structural shape of pads in the decoder region, leading to bridge failures and increased complexity in reducing the chip size and area of the peripheral circuit region.
Innovation Solution
A padless semiconductor device structure is fabricated by forming conductive lines in a first region extending to multiple second regions, with alternating conductive lines and interlayer insulating layers, and selectively etching to create open regions for contact plugs, simplifying the process and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If pads are formed in the decoder region with 90° bends to provide spacing, then the structural shape requirement is satisfied, but pattern breaking occurs at the bends due to insufficient photolithography margin
Solution Approach 1:
The invention extracts and eliminates the pad structure from the decoder region entirely. Instead of forming pads with 90° bends, the conductive layer is directly patterned to extend from the cell region into the peripheral circuit region, removing the problematic bent structure that caused pattern breaking while maintaining the necessary electrical connections.
Solution Approach 2:
Instead of forming pads first and then creating conductive lines, the invention inverts the approach by directly forming conductive lines that extend continuously from the cell region through the peripheral circuit region without intermediate pad structures, thereby eliminating the bending issue entirely.
2Reliability
If pads are uniformly disposed at the ends of conductive lines to ensure electrical connection, then reliability is improved, but the area of the peripheral circuit region increases making chip size reduction difficult
Solution Approach 1:
The invention merges the function of pads with the conductive lines themselves. The conductive layer is configured to extend continuously from the cell region into the peripheral circuit region, combining the electrical connection function previously separated into distinct pad structures with the conductive line function, thereby eliminating the need for additional pad area.
Solution Approach 2:
The conductive layer serves multiple functions: it acts as both the conductive line for signal transmission and as the pad structure for electrical connection to external terminals. This multi-functional design eliminates the need for separate pad structures, reducing the peripheral circuit region area while maintaining reliable electrical connections.
3Length of moving object
If double spacer patterning technology is applied to meet decreased design rules, then feature size is reduced, but patterning margin is further reduced making bridge failures more likely
Solution Approach 1:
The invention extracts and eliminates the problematic 90° bent pad structures that are particularly susceptible to bridge failures. By removing these sharp corners and bends from the design, the patent reduces the risk of pattern breaking and bridge formation during photolithography, even when using advanced double spacer patterning techniques with tight design rules.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The padless structure enhances integration and reduces the area of the peripheral circuit region, simplifying the fabrication process and improving manufacturing yield by eliminating the need for pads, thus reducing chip size and process complexity.
Implementation Method 1
the conductive layer 12 is etched using the first and second mask patterns 14 and 15 as an etch mask to form pads 12B in the second region while forming conductive lines 12A in the first and second regions
Data Source
AI summary
A substrate having a first region and second regions disposed on two sides of the first region; a first group of conductive lines extending from the first region to the second regions on the substrate; a second group of conductive lines alternating with the first group of times and extending from the first region to the second regions on the substrate; interlayer insulating layers formed over the substrate; insulating layers formed in first open regions of the interlayer insulating layers and the first group of conductive lines in the second region; and contact plugs contacting second group of conductive line formed in second open regions of the interlayer insulating layer in the second region.