Page-Based Memory Compression for Cache Efficiency
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Solution Overview
Problem
Processing systems face performance bottlenecks and reliability issues due to cache misses and uneven wear in higher-level memories, primarily caused by space and power limitations in memory hierarchies, which lead to increased latency and reduced write endurance.
Innovation Solution
Implementing a memory hierarchy with row-based and page-based compression schemes, where data is compressed in lower-level memories, allowing for more efficient storage and retrieval, reducing the need for higher-level memory accesses and mitigating wear-out through wear-leveling techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache size is increased to reduce cache misses, then memory access reliability is improved, but space and power limitations are exceeded
Solution Approach 1:
The patent changes the parameter of data representation by applying compression algorithms to reduce the amount of data stored in the cache. This allows the same physical cache size to effectively store more data, reducing cache misses without increasing the actual cache area or power consumption.
2Productivity
If more data is stored in lower-level memory to reduce cache misses, then memory access efficiency is improved, but space limitations are exceeded
Solution Approach 1:
The patent applies compression to change the parameter of data size, allowing more data to be stored in the same physical space. This increases the effective storage capacity of lower-level memory without adding physical memory components.
3Reliability
If write accesses to higher-level memory are increased to maintain data consistency, then system reliability is improved, but wear-out increases
Solution Approach 1:
The patent changes the data size parameter through compression, which reduces the number of write operations required to maintain data consistency in higher-level memory. Fewer write accesses extend the lifespan of the memory while maintaining data consistency through proper cache coherence protocols.
Data Source
AI summary
A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory.