Page Buffer Biasing Control for Non-Volatile Memory Read Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As flash memory devices become denser, the reduced distance and increased resistance of bit lines lead to higher read operation errors, especially in multiple level memory cells, due to incorrect biasing conditions and aging cells with deviating threshold voltages.
Innovation Solution
A method to adjust the bias voltage of the switching element in the page buffer based on inputted address information using a look-up table and matching logic, which groups word-lines by their I-V characteristics to account for varying resistive values across different address zones, ensuring precise control during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory devices are made denser to increase storage capacity, then storage capacity is improved, but bit line resistance increases causing higher read operation errors
Solution Approach 1:
The patent applies local quality by adjusting the bias voltage of the switching element based on the specific address zone being accessed. Different bit line regions (local areas) receive different bias voltages tailored to their resistance characteristics, rather than using a uniform voltage across the entire memory array. This localized adaptation compensates for the increased resistance in specific regions caused by higher density, thereby maintaining read operation accuracy.
Solution Approach 2:
The patent changes the bias voltage parameter dynamically based on the address zone. The controlling block modifies the bias voltage level according to the resistance characteristics of different bit line regions, allowing the system to adapt to varying electrical conditions across the memory array. This parameter adjustment compensates for resistance variations induced by high-density configuration.
2Quantity of substance
If bit line resistance increases due to higher density, then storage capacity is improved, but biasing conditions become incorrect leading to read errors
Solution Approach 1:
The patent introduces dynamic biasing control where the bias voltage is not fixed but is adjusted based on the address zone being accessed. The controlling block dynamically modifies the bias voltage parameter according to the resistance characteristics of different bit line regions, enabling the system to adapt to changing electrical conditions and maintain proper biasing conditions across the entire memory array.
Solution Approach 2:
The patent implements a feedback mechanism where the address information is used to determine the appropriate bias voltage level. The controlling block receives address information, identifies the corresponding address zone, and adjusts the bias voltage accordingly. This feedback loop ensures that the biasing conditions are continuously optimized based on the actual electrical characteristics of the accessed memory region.
3Duration of action of stationary object
If aging cells are used, then device longevity is improved, but threshold voltages deviate causing increased read errors
Solution Approach 1:
The patent changes the bias voltage parameter to compensate for threshold voltage deviations in aging cells. By adjusting the bias voltage based on the address zone and the known characteristics of aging cells in that region, the system maintains accurate read operations despite threshold voltage shifts that occur over time. This parameter adaptation allows the device to maintain performance throughout its operational lifetime.
4Reliability
If address zones are grouped by I-V characteristics to account for resistance variations, then read accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory array into multiple address zones based on I-V characteristics and resistance variations. Each address zone is assigned a specific bias voltage level tailored to its electrical characteristics. This segmentation allows the system to manage complexity by dividing the large memory array into smaller, more manageable regions with relatively uniform characteristics, making the biasing control more tractable while improving read accuracy.
Data Source
AI summary
A controlling block for a non-volatile memory device including a switching element coupling a bit-line with the corresponding page buffer, includes: a look-up table configured to store a plurality of address zones; and a matching logic configured to match one address zone among the plurality of address zones based on an inputted row address and generate a bias voltage, based on the address zone, to the switching element for reading operation of the non-volatile memory, wherein the plurality of address zones are defined by grouping word-lines having a I-V characteristic which differs for a current value different from a prefixed value.