Page Buffer Bit Line Precharge for Program Verify Time Reduction
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in program verification time due to the sequential application of verify voltages for multiple program states, which prolongs the overall program verify operation.
Innovation Solution
A page buffer system that precharges bit lines to specific voltage levels and simultaneously verifies at least two program states using a single verify voltage, reducing the program verify operation time by optimizing the bit line precharge and evaluation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If verify voltages are sequentially applied for multiple program states, then verification accuracy is maintained, but program verify operation time is prolonged
Solution Approach 1:
The patent applies preliminary action by precharging bit lines to specific voltage levels (first set voltage or second set voltage) before the verify operation based on the program state. This precharge preparation enables faster subsequent verification by having the bit lines ready at appropriate voltage levels, reducing the overall verify time while maintaining accuracy through state-dependent precharging
Solution Approach 2:
The patent implements periodic action by applying a single verify voltage periodically to verify multiple program states in sequence rather than applying different verify voltages continuously. The bit line potential is periodically adjusted between first and second set voltages corresponding to different program states, enabling time-efficient verification while maintaining measurement precision through structured periodic voltage application
2Speed
If bit line precharge is optimized for multiple program states, then verify operation speed increases, but circuit complexity increases
Solution Approach 1:
The patent applies universality by designing the bit line controller to handle multiple program states using a unified control mechanism. The same bit line and verify voltage are used for verifying multiple program states by adjusting the bit line potential between first and second set voltages, rather than requiring separate verification circuits for each state. This multi-functional approach increases speed while controlling complexity through resource sharing
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the bit line potential between first set voltage and second set voltage based on the program state being verified. This parameter adjustment enables the same hardware circuit to efficiently verify multiple program states with different threshold voltage distributions, increasing verify speed without proportionally increasing circuit complexity through parameter-based adaptation rather than structural multiplication
Data Source
AI summary
The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line of a memory block and precharging the bit line by applying one of a first set voltage and a second set voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verify operation, and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verify data according to a potential level of the main sensing node during the program verify operation.