Page Buffer Line Reduction via Odd-Even Bitline Segmentation
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Solution Overview
Problem
In NAND flash memory devices, the high number of lines in the page buffer during bit-line stress testing increases the complexity and reduces operational reliability, making it difficult to detect defects effectively.
Innovation Solution
The semiconductor device organizes bit lines into alternating even and odd groups, with page buffers arranged contiguously within each group, reducing the overall number of lines in the page buffer and allowing for efficient stress testing by grouping and controlling even and odd lines separately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If the page buffer includes all bit lines for stress testing, then defect detection capability is improved, but the number of lines increases complexity and reduces operational reliability
Solution Approach 1:
The patent segments bit lines into odd and even groups, and further divides them into first and second groups based on their connection patterns. This segmentation allows the page buffer to test specific bit line groups independently, reducing the total number of lines that need to be simultaneously managed while maintaining comprehensive defect detection capability through systematic testing of segmented portions.
Solution Approach 2:
The patent merges odd bit lines and even bit lines into alternating sequences, creating a structured arrangement where odd and even bit lines are interspersed. This merging strategy allows for compact page buffer design where multiple bit lines can be tested through coordinated control, reducing the effective number of independent lines while maintaining testing coverage.
2Difficulty of detecting and measuring
If the page buffer includes all bit lines for stress testing, then defect detection capability is improved, but operational reliability is reduced
Solution Approach 1:
By segmenting bit lines into odd and even groups with distinct connection patterns, the patent enables selective testing of specific segments. This reduces the impact of any single bit line failure on overall system reliability while maintaining the ability to detect defects through systematic segmentation and targeted testing of individual segments.
Solution Approach 2:
The patent introduces a dimensional organization where bit lines are arranged in alternating odd-even sequences rather than simple sequential ordering. This dimensional reorganization creates redundant connection paths and allows for more robust error detection and isolation, improving operational reliability while maintaining defect detection capability.
3Shape
If bit lines are arranged in alternating odd and even groups, then layout structure is improved, but the organization becomes more complex
Solution Approach 1:
The patent employs asymmetric connection patterns where odd bit lines connect to first connection lines and even bit lines connect to second connection lines in an alternating sequence. This asymmetric organization creates a regular yet non-uniform structure that improves layout efficiency and signal routing while the alternating pattern provides inherent organizational simplicity through its repetitive nature.
Data Source
AI summary
A semiconductor device including a page buffer is disclosed, which reduces the number of lines of the page buffer. The semiconductor device includes a plurality of bit lines, classified into a first group and a second group, that are arranged alternating, a first page buffer circuit coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines, and a second page buffer circuit coupled to the plurality of connection lines. Each of the first group and the second group includes a plurality of bit-line pairs classified into odd bit lines and even bit lines. The plurality of connection lines includes odd connection lines and even connection lines, and odd connection lines corresponding to the odd bit lines are arranged contiguous to each other, and even connection lines corresponding to the even bit lines are arranged contiguous to each other.