Page Buffer Timing Control for Long Bit Line Memory Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the degree of integration of memory devices increases, leading to a higher number of memory cells and longer bit and local lines, electric delays occur during program, read, or erase operations, which deteriorate the reliability and efficiency of the memory device.
Innovation Solution
A memory device that adjusts voltages applied to bit lines based on their distance from the row decoder, using a page buffer control circuit to manage voltage levels and application times, ensuring consistent operation across varying distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of the memory device increases, then the number of memory cells increases, but electric delay occurs in program, read, or erase operations
Solution Approach 1:
The bit lines are divided into multiple groups based on their distance from the row decoder. Each group is assigned to a separate page buffer, allowing independent voltage application timing. This segmentation enables differential voltage control strategies for different bit line groups, optimizing the balance between integration scale and operation speed.
Solution Approach 2:
The page buffer control circuit pre-adjusts the voltage application timing for each bit line group based on their respective distances from the row decoder. By preliminarily determining the optimal voltage application sequence, the circuit compensates for electric delay effects before operations begin, ensuring synchronized voltage arrival at memory cells across different bit line groups.
2Quantity of substance
If the number or length of bit lines and local lines increases, then the number of memory cells increases, but electric delay occurs
Solution Approach 1:
Different voltage application timings are assigned to different bit line groups based on their local characteristics (distance from row decoder). The page buffer control circuit applies voltages with locally optimized timing to each bit line group, ensuring reliable operation despite varying line lengths and electrical characteristics across the memory device.
3Length of stationary object
If the length of bit lines increases, then the number of memory cells increases, but the time required for operations increases
Solution Approach 1:
The voltage application timing is dynamically adjusted for each bit line group based on their distance from the row decoder. Longer bit lines receive voltages at different times compared to shorter bit lines, creating a dynamic timing scheme that compensates for signal propagation delays and maintains high operation speed despite increased line lengths.
Data Source
AI summary
A memory device, and an operating method of the memory device, includes a voltage generator for generating operating voltages and a row decoder for transmitting the operating voltages to a memory block through local lines. The memory device also includes page buffers connected to the memory block through bit lines, the page buffers applying voltages to the bit lines in response to page buffer control signals. The memory device further includes a page buffer control circuit for outputting the page buffer control signals by adjusting levels of the voltages and times at which the voltages are applied to the bit lines according to distances of the bit lines from the row decoder.