Page Buffer Erase Circuit for B-VNAND Bonding Pad Stress Testing
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Solution Overview
Problem
Misalignment between bonding pads in 3D non-volatile memory devices can lead to material migration, and existing stress testing methods are inadequate for both bit lines and bonding pads in B-VNAND structures.
Innovation Solution
A page buffer circuit design where adjacent erase transistors connected to different erase voltage lines are activated by the same gate signal, allowing for simultaneous stress testing of bit lines and bonding pads, with one erase transistor connected between a bit line and an erase voltage line and the other between a different erase voltage line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding pads are disposed adjacent to each other in B-VNAND structure, then material migration occurs due to misalignment, but stress testing capability is improved
Solution Approach 1:
The patent divides the bonding pad structure into separate first and second bonding pads disposed adjacent to each other, each connected to different erase voltage lines. This segmentation allows independent voltage application to each bonding pad, enabling stress testing while maintaining structural integrity to prevent material migration.
Solution Approach 2:
The patent applies different voltages to different bonding pads (first erase voltage to first bonding pad, second erase voltage to second bonding pad) based on their specific positions and functions. This local quality approach enables targeted stress testing of adjacent bonding pads while maintaining appropriate voltage levels to prevent harmful material migration.
2Reliability
If different erase voltage lines are used for adjacent erase transistors, then stress testing of bonding pads is enabled, but circuit complexity increases
Solution Approach 1:
The patent designs the erase voltage lines to serve multiple functions: during normal operation, they provide erase voltage to erase transistors; during stress testing mode, they apply different voltages to adjacent bonding pads. This multi-functionality enables stress testing capability without requiring completely separate testing circuitry, thus managing complexity.
Solution Approach 2:
The patent implements dynamic voltage application where the first and second erase voltage lines can be configured to provide different voltages to bonding pads during stress testing mode. This dynamic configuration allows the same circuit structure to adapt between normal operation and stress testing functions.
3Area of stationary object
If bonding pads are disposed adjacent to each other, then space efficiency is improved, but misalignment between bonding pads occurs
Solution Approach 1:
The patent incorporates test modes that apply different voltages to adjacent bonding pads before actual bonding operations. This preliminary action detects potential misalignment or material migration risks, allowing corrective measures to be taken before manufacturing defects occur.
Solution Approach 2:
The patent implements a feedback mechanism where the stress testing results from applying different voltages to adjacent bonding pads provide information about alignment quality. This feedback allows for detection and correction of misalignment issues, ensuring manufacturing precision despite close spacing.
Data Source
AI summary
A non-volatile memory device is provided, including a first bit line, a second bit line, a first page buffer including a first erase transistor connected to the first bit line via a first bonding pad, and a second page buffer including a second erase transistor connected to the second bit line via a second bonding pad, and a plurality of bonding pads including a first bonding pad and a second bonding pad. The first erase transistor is driven based on a first erase control signal and is connected between the first bit line and the first erase voltage line. The second erase transistor is driven based on a first erase control signal and is connected between the second bit line and the second erase voltage line different from the first erase voltage line. The first bonding pad and the second bonding pad are disposed adjacent to each other.