Page Buffer Cache Extension for SLC Memory Metadata Thrashing
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Solution Overview
Problem
Memory sub-system controllers in systems like UFS lack sufficient cache due to the high cost of SRAM and TCM, leading to increased data thrashing and reduced quality-of-service, as they are limited to less efficient cache solutions.
Innovation Solution
Treat page buffers coupled to SLC memory as an extension of the sub-system cache, utilizing them to store metadata during operations, thereby expanding cache capacity and reducing data traffic across the ONFI bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM or TCM is used as cache in memory sub-system controllers, then cache speed and performance are improved, but system cost increases significantly
Solution Approach 1:
The patent uses SLC memory page buffers as a disposable/temporary cache extension rather than investing in expensive SRAM or TCM. The SLC page buffers serve as a cost-effective alternative that provides sufficient caching capability for metadata operations without the high cost of traditional high-speed cache memory.
Solution Approach 2:
The patent makes SLC page buffers serve dual functions: their primary function for data storage and a secondary function as cache memory for metadata operations. This multi-functionality eliminates the need for separate cache hardware, reducing overall system cost while maintaining performance.
2Productivity
If cache capacity is increased to reduce data thrashing, then quality-of-service improves, but the cost of SRAM or TCM increases
Solution Approach 1:
The patent nests the cache function within the existing SLC page buffer structure. Instead of adding a separate cache layer, the cache functionality is embedded within the already-present page buffers, effectively creating a nested arrangement where one function (caching) is contained within another structure (page buffers).
Solution Approach 2:
The patent changes the operational parameters of SLC page buffers by allocating specific page buffers exclusively for cache operations during SLC operations. This parameter change transforms ordinary page buffers into functional cache memory without requiring additional hardware resources.
3Quantity of substance
If page buffers are used as cache extension, then cache capacity increases and data thrashing reduces, but device complexity increases
Solution Approach 1:
The patent implements self-service mechanisms where the memory sub-system controller automatically detects when SLC operations are occurring and autonomously allocates appropriate page buffers for cache operations. This self-service approach minimizes the need for external intervention or complex manual configuration, reducing operational complexity despite the enhanced functionality.
Data Source
AI summary
A system includes a memory device comprising an array of memory cells coupled with a plurality of page buffers. At least a portion of the array is configured as single-level cell memory. A processing device is coupled to the memory device and includes cache. The processing device detects demand for the cache during a memory operation requiring access to the single-level cell memory. Detecting the demand can include determining an amount of metadata required to be accessed or updated based on a type of the memory operation. The processing device causes, based on the demand, the metadata associated with the memory operation to be moved from one of the cache or the array of memory cells to one or more page buffers of the plurality of page buffers.