Page Buffer Temporary Cache for Memory Controller Storage

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Solution Overview

Problem

In memory systems, existing technologies do not effectively utilize page buffers as temporary caches, leading to inefficiencies in data storage and retrieval, particularly in flash memory devices where data is not efficiently managed between the controller's storage and the page buffer before programming into memory cells.

Innovation Solution

A method and apparatus that utilize page buffers as temporary caches by implementing 'burst data load' and 'burst data read' commands to transfer data from the controller's storage to the page buffer and back, allowing for data to be stored temporarily without being programmed into memory cells, thereby freeing up storage space and enhancing read and program performances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is continuously stored in the controller's data storage for programming into memory cells, then data availability for programming is maintained, but storage space in the controller is consumed and cannot be reused

Engineering Contradiction:
Improvestorage space in controllerVSAvoiddata transfer time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent applies preliminary action by transferring data from the controller's data storage to the page buffer in advance, before the data is actually needed for programming operations. This allows the controller to free up storage space while the data remains readily accessible in the page buffer for subsequent programming or re-transfer operations, thus resolving the contradiction between storage space availability and data accessibility.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If data is transferred from controller to page buffer, then storage space in controller is freed up, but data must be transferred back to controller when needed

Engineering Contradiction:
Improvestorage space in controllerVSAvoiddata management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms through status flags and control logic that track the location and state of data between the controller and page buffer. The system automatically manages data transfer operations based on programming needs, using feedback signals to determine when data should be in the page buffer versus when it should be transferred back to the controller, thereby simplifying the overall data management complexity despite the additional transfer capability.

Inventive Principle:
Principle #23Feedback

3Productivity

If page buffer is used as temporary cache, then read and program performances are improved, but additional control operations are required

Engineering Contradiction:
Improveread and program performanceVSAvoidoperation simplicity
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The patent applies universality by designing the page buffer to serve multiple functions: it acts as a temporary cache for data during programming operations, a storage location for data to be programmed, and a buffer for data read operations. The same page buffer structure and control logic handle all these different operations, eliminating the need for separate dedicated buffers for each function and thereby improving read and program performance without proportionally increasing operational complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9836391B2System and method of page buffer operation for memory devices
Publication Date: 2017.12.05 MOSAID TECH
  • US9836391B2 patent drawing
  • US9836391B2 patent drawing
  • US9836391B2 patent drawing

AI summary

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.