Page Buffer Cache Release for Memory Write Performance
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Solution Overview
Problem
In memory devices, particularly in multi-level cell (MLC) and tri-level cell (TLC) systems, there is a time delay between programming different groups of memory cells due to the sequential entry of data into page buffers, which hampers write performance and efficiency.
Innovation Solution
Implementing a method where the cache associated with each page of data is incrementally released as cells are programmed to target states, allowing concurrent data entry and programming, thereby minimizing or eliminating the time delay between programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is entered into page buffers sequentially before programming, then data integrity is ensured, but write performance deteriorates due to time delays between programming operations
Solution Approach 1:
The patent applies preliminary action by pre-loading data into page buffers before programming operations begin. Multiple pages of data are entered into the page buffer in advance, so that when programming of one group of memory cells completes, the next page of data is already ready in the buffer, eliminating idle time and enabling continuous programming operations without waiting for sequential data entry
Solution Approach 2:
The patent implements continuity of useful action by overlapping data entry and programming operations. While programming is正在进行 for one set of memory cells, data for subsequent pages is simultaneously being entered into the page buffer. This parallel execution ensures that the programming operation continues without interruption, maintaining continuous useful action and maximizing write performance
2Productivity
If multiple pages of data are pre-loaded into page buffers, then programming speed improves through concurrent operations, but device complexity increases due to buffer management requirements
Solution Approach 1:
The patent applies segmentation by dividing the page buffer into multiple separate buffers, with each buffer dedicated to storing a specific page of data. This segmentation allows independent management of each buffer, simplifying the control logic compared to managing a single large buffer. Each buffer can be filled and programmed independently, reducing the complexity of coordinating data movement and buffer state management while enabling parallel programming operations
Data Source
AI summary
Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states.