Page Buffer Circuit for Nonvolatile Memory Program Speed Control
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Solution Overview
Problem
The existing double verification method for programming nonvolatile memory cells extends program time and has limitations in narrowing the threshold voltage distribution width due to repeated verification operations, which affects the reliability of the memory device.
Innovation Solution
A page buffer circuit with a sense unit, latch unit, and bit line voltage control unit that performs multiple verification operations to classify memory cells into groups based on program speed, adjusting the bit line voltage to control program speeds and narrow the threshold voltage distribution by using incremental verification voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a double verification method is used to control program speeds of memory cells, then the threshold voltage distribution width is narrowed, but the program time is extended
Solution Approach 1:
The patent segments memory cells into multiple groups based on their program speeds by performing multiple verification operations. Each group receives different bit line voltages during programming, allowing differentiated control of program speeds to narrow threshold voltage distribution while optimizing overall program time
Solution Approach 2:
The patent changes the bit line voltage parameter dynamically based on verification results. By adjusting bit line voltage to different levels (e.g., 0V, Vpp/2, Vpp) for different memory cell groups, the program speed of each group is controlled to achieve narrow threshold voltage distribution
2Manufacturing precision
If repeated verification operations are performed to narrow threshold voltage distribution, then the threshold voltage distribution width is narrowed, but the program time is extended
Solution Approach 1:
The patent performs preliminary verification operations before the main programming process to classify memory cells into groups. This preliminary classification allows subsequent programming to be optimized for each group, narrowing threshold voltage distribution without requiring repeated full verification cycles
Solution Approach 2:
The patent dynamically adjusts bit line voltage based on real-time verification results. The voltage level applied to each memory cell group is dynamically changed according to its program speed characteristics, enabling efficient control of program speed and threshold voltage distribution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces program time and effectively narrows the threshold voltage distribution width by controlling program speeds of memory cells, enhancing the reliability of the nonvolatile memory device.
Implementation Method 1
The sense unit is configured to couple a bit line and a sense node in response to a sense control signal to detect a voltage of the selected bit line
Implementation Method 2
The latch unit includes a plurality of latch circuits that are configured to latch data to be programmed into a memory cell or that are coupled to the sense node in order to store data programmed into a memory cell
Implementation Method 3
The bit line voltage control unit coupled to the selected bit line is configured to control a voltage level of the sense control signal in order to transfer a bit line voltage to the selected bit line
Implementation Method 4
The bit line voltage control unit is configured to classify program states of memory cells into first to nth groups by performing first to nth verification operations
Implementation Method 5
the program operation of a flash memory cell is generally performed by applying a high positive voltage to the control gate so that Fowler-Nordheim (F-N) tunneling is generated between the floating gate and the substrate
Implementation Method 6
In F-N tunneling, an electric field of a high voltage applied to the control gate causes electrons of the bulk region to be accumulated in the floating gate, and so the threshold voltage of the memory cell rises
Data Source
AI summary
A page buffer circuit comprises a sense unit, a latch unit, and a bit line voltage control unit. The sense unit is configured to couple a bit line and a sense node in response to a sense control signal in response to the sense control signal. The latch unit includes a plurality of latch circuits configured to latch data programmed or to be programmed. The bit line voltage control unit is configured to classify program states of memory cells, coupled to the selected bit line, into first to nth groups by performing first to nth verification operations after a first program operation of a program operation and is configured to control a voltage level of the sense control signal in order to transfer a bit line voltage to the selected bit line.