Page Buffer Circuit Suspend Read Operation via Caching Latch

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Solution Overview

Problem

Nonvolatile memory devices face limitations in performing suspend read operations due to the need for additional storage space and separate latch circuits, which restricts chip area and operational efficiency.

Innovation Solution

A page buffer circuit incorporating a sensing latch circuit and a caching latch circuit allows for suspend read operations without requiring additional storage space, utilizing the caching latch circuit to sense and output data directly during suspend read operations, thereby eliminating the need for separate latch circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a separate latch circuit or storage circuit is added for suspend read operation, then the suspend read operation can be supported, but the chip area increases

Engineering Contradiction:

Improvesuspend read operation supportVSAvoidchip area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The caching latch circuit is designed to perform multiple functions: it acts as a data cache during normal read operations and serves as the storage circuit for suspend read operations. This multi-functional design eliminates the need for a separate storage circuit, thereby supporting suspend read operations without increasing chip area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the storage function for suspend read operations into the existing caching latch circuit by adding a control unit. This consolidation combines the caching function and suspend read storage function into a single circuit structure, avoiding the need for additional separate storage circuits and reducing chip area.

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If additional storage space is provided for suspend read operation, then the suspend read operation can be performed, but the device complexity increases

Engineering Contradiction:

Improvesuspend read operation supportVSAvoidlatch circuit structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The control unit enables the caching latch circuit to switch between different operational modes (normal read caching and suspend read storage), allowing a single circuit structure to handle multiple operations without requiring separate dedicated circuits for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The control unit is configured to transfer data to the caching latch circuit in advance during normal read operations, preparing the data for potential suspend read operations. This preliminary action allows the circuit to be ready for suspend read operations without requiring additional storage infrastructure.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12062399B2Page buffer circuit, semiconductor memory apparatus including page buffer circuit, and operating method of semiconductor memory apparatus

Publication Date: 2024.08.13 SK HYNIX INC

AI summary

A page buffer circuit includes a sensing latch circuit and a caching latch circuit. The sensing latch circuit is configured to receive and sense data that is stored in a memory cell during a normal read operation. The caching latch circuit is configured to receive and sense the data that is stored in the memory cell during a suspend read operation.