Page Buffer Circuit Single Verify Voltage NAND Flash
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Solution Overview
Problem
Existing NAND flash memory devices require multiple verify voltages to verify the program state of memory cells, leading to increased program duration and inefficiency.
Innovation Solution
A memory device with a page buffer circuit that includes a sensing node, a first latch circuit to latch the programmed state of an adjacent memory cell, and a charge and discharge circuit to control the discharge duration of the sensing node based on the programmed state, allowing a single verify voltage to be used for program verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple verify voltages are used to verify the program state of memory cells, then verification accuracy is improved, but program duration is increased
Solution Approach 1:
The patent changes the parameter of verify voltage from multiple discrete voltage levels to a single voltage level, while compensating by adjusting the discharge duration parameter of the sensing node to achieve the same verification accuracy with shorter program time
Solution Approach 2:
The patent performs preliminary action by latching the programmed state of the first memory cell before verification, and uses this information to pre-determine the discharge duration of the sensing node, enabling single-voltage verification without sacrificing accuracy
2Reliability
If discharge duration of sensing node is extended to compensate for parallel channel charge loss, then data retention performance is improved, but verification time is increased
Solution Approach 1:
The patent adjusts the discharge duration parameter of the sensing node based on the latched programmed state of the adjacent memory cell, optimizing the balance between charge loss compensation and verification time by dynamically setting the discharge duration to the minimum necessary value
Solution Approach 2:
The patent uses feedback from the latched programmed state of the first memory cell to control the discharge duration of the sensing node during verification of the second memory cell, creating a closed-loop system that optimizes both data retention and verification speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly shortens the program duration by allowing a single verify voltage to be used, while improving data retention performance by compensating for parallel channel charge loss.
Implementation Method 1
a sensing node, coupled to the bit line; a charge and discharge circuit, coupled to the sensing node, and configured to: charge the sensing node, and discharge the sensing node
Data Source
AI summary
A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a first memory cell and a second memory cell coupled to a same bit line and being adjacent. The peripheral circuit includes a page buffer circuit. The page buffer circuit includes: a sensing node coupled to the bit line; a first latch circuit coupled to the sensing node, and configured to latch a programmed state of first memory cell; a charge and discharge circuit coupled to the sensing node, and configured to: charge the sensing node, and discharge the sensing node, wherein discharge duration of the sensing node is related to the programmed state; and a second latch circuit coupled to the sensing node, and configured to latch, according to a voltage value of the sensing node after the discharge duration, information of whether second memory cell passes program verification.