Page Buffer High-Voltage Circuit Contact Pad Orientation
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Solution Overview
Problem
The increasing demand for higher integration and miniaturization in semiconductor memory devices leads to challenges in maintaining reliable connections between bit lines and contact pads, with decreasing overlay margins potentially causing coupling failures due to the narrowing spacing between these components.
Innovation Solution
The semiconductor memory device design includes a page buffer high-voltage circuit divided into regions with page buffer high-voltage elements coupled to bit lines and contact pads, where the contact pads are arranged in a direction intersecting with the bit lines, allowing for a larger width compared to the pitch of the bit lines, and coupling lines are strategically placed to increase spacing and reduce interference, thereby enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between bit lines and contact pads is decreased to achieve higher integration, then the device capacity increases, but the overlay margin decreases leading to coupling failures
Solution Approach 1:
The contact pads are arranged in a direction intersecting with the bit lines, changing the spatial relationship from parallel to perpendicular/intersecting. This dimensional change allows the width of contact pads to be larger than the pitch of bit lines while maintaining adequate spacing, thus improving overlay margin without sacrificing integration density
Solution Approach 2:
The page buffer high-voltage circuit is divided into multiple regions with different configurations. Specifically, contact pads are strategically positioned in certain regions with optimized dimensions and orientations, allowing local optimization of overlay margin in critical areas while maintaining overall high integration
2Reliability
If the width of contact pads is increased to improve coupling reliability, then the overlay margin improves, but the device area increases
Solution Approach 1:
By arranging contact pads in a direction intersecting with bit lines rather than parallel, the design utilizes the second dimension more effectively. This allows contact pad width to exceed bit line pitch in the intersecting direction without proportionally increasing overall device area, as the spacing optimization occurs locally at critical coupling points
Solution Approach 2:
The page buffer high-voltage circuit is segmented into multiple regions, with contact pads distributed strategically throughout. This segmentation allows the contact pad structure to be optimized locally for reliability while the overall device area is controlled through selective placement and regional optimization rather than uniform expansion
Data Source
AI summary
A semiconductor memory device includes a plurality of bit lines extending in a first direction, and arranged in a second direction intersecting with the first direction, a page buffer high-voltage circuit divided into a plurality of page buffer high-voltage regions arranged in the first direction, each of the plurality of page buffer high-voltage regions including a plurality of page buffer high-voltage elements, each page buffer high-voltage element coupled to one of the plurality of bit lines, and a contact pad unit including a plurality of contact pads, each contact pad coupled to one of the plurality of page buffer high-voltage elements. The contact pad unit is arranged, in the first direction, between two of the plurality of page buffer high-voltage regions.