Page Buffer Precharging Optimization via Dynamic Current Control
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Solution Overview
Problem
Current page buffers in memory devices require significant time for precharging operations during data reading, which affects performance and efficiency.
Innovation Solution
A page buffer design that includes a charging circuit, a first storage circuit to determine the state of a selected memory cell during precharging, and a selection circuit to adjust the control voltage for the switch element between the charging circuit and the bit line, allowing for reduced charging current based on the stored data, thereby optimizing the precharging time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a page buffer uses a conventional charging circuit to charge a bit line during a precharging period, then the bit line voltage can be adjusted, but the precharging time becomes excessively long, degrading memory device performance
Solution Approach 1:
The patent applies dynamics by making the charging current variable rather than fixed. The control circuit dynamically adjusts the magnitude of the charging current based on the initial state of the bit line voltage, transitioning from a static charging approach to a dynamic one that adapts to real-time conditions to optimize precharging speed while reducing total precharging time
Solution Approach 2:
The patent changes the parameter of charging current magnitude based on the detected bit line voltage state. By detecting whether the bit line voltage is above or below a reference voltage and adjusting the charging current magnitude accordingly, the system optimizes the precharging process to complete faster while ensuring the bit line reaches the required voltage level
2Productivity
If a page buffer charges all bit lines with the same current regardless of memory cell state, then the charging process is simple, but it fails to optimize precharging time for different cell states
Solution Approach 1:
The patent applies local quality by providing different charging currents to different bit lines based on their specific conditions. Instead of a uniform charging approach, the control circuit detects the state of each bit line and applies a locally optimized charging current magnitude, allowing each bit line to be charged at the optimal rate for its specific state
Solution Approach 2:
The patent implements feedback by having the control circuit detect the voltage state of the bit line during precharging and use this information to adjust the charging current magnitude. This closed-loop feedback mechanism enables the system to automatically optimize the precharging process based on real-time conditions, improving reading operation efficiency while managing complexity through intelligent control
Data Source
AI summary
A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.