Page Buffer Block Verification Error Removal Circuit
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in accurately counting off-cells due to verification signal errors caused by defective circuits or lines, which affect the reliability of memory operations.
Innovation Solution
A memory device with a page buffer block that includes a verification error removal circuit, which uses a first latch to store state information about defective bit lines or page buffers and controls the output path of the verification signal to prevent errors from being used in the counting operation, ensuring accurate verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If verification operation is performed using conventional circuits, then memory operation speed is maintained, but verification signal errors occur due to defective circuits or lines affecting counting accuracy
Solution Approach 1:
The patent applies preliminary action by performing a test operation before the actual verification operation to identify defective bit lines or page buffers. The test operation activates test word lines and applies test voltages to detect defects in advance, storing the results in a defect map. This allows the system to compensate for defects during the subsequent verification operation, ensuring accurate off-cell counting despite potential circuit or line defects.
2Measurement precision
If defective bit lines or page buffers are not compensated, then device complexity is low, but measurement precision of off-cell counting deteriorates
Solution Approach 1:
The patent introduces an intermediary defect map that stores information about defective bit lines or page buffers. This defect map acts as a mediator between the test operation results and the verification operation. During verification, the control logic references the defect map to determine which bit lines or page buffers should be excluded from the counting process, thereby compensating for defects without requiring complex hardware modifications to the fundamental verification circuitry.
3Reliability
If test operation is performed to identify defects, then verification accuracy is improved, but operation time increases due to additional testing steps
Solution Approach 1:
The test operation is performed as a preliminary action during manufacturing or initialization to identify defective bit lines or page buffers. The results are stored in a defect map that is retained for use during subsequent verification operations. This approach amortizes the time cost of defect identification over multiple verification operations, making the initial time investment worthwhile by ensuring reliable and accurate verification throughout the device's operational life.
Data Source
AI summary
A memory device according to an embodiment includes a memory cell array including a plurality of memory cells, a control logic configured to control a verification operation for the plurality of memory cells, a page buffer block including a plurality of page buffers connected to the memory cell array through bit lines, a page buffer decoder that outputs, through an output line. a verification signal generated from at least one of outputs of the plurality of page buffers by a verification operation, and a verification error removal circuit connected to the output line and configured to control an output path of the verification signal to the control logic.