Page Buffer Gate Contact Layout for Scaled 3D NAND CuA
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Solution Overview
Problem
Current 3D NAND memory devices face challenges in scaling the page buffer (PB) area to accommodate increasing bit density and functionality, leading to significant consumption of CuA space and increased complexity in photolithographic processes like 193i lithography, which are costly and complex.
Innovation Solution
Implementing a process flow that uses 365 i-line photolithography to selectively open the page buffer region, followed by a dry etch to remove the blanket deposited conductive material, thereby simplifying the process and reducing the complexity of stringent CD control and etch depth control, allowing for the formation of gate contacts directly to polysilicon gates in the PB region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 193i lithography is used to scale the page buffer area, then the page buffer can accommodate increasing bit density and functionality, but the process complexity and cost increase significantly
Solution Approach 1:
The patent extracts the page buffer region from the general CuA region and processes it separately using selective opening. This allows the PB region to be accessed and modified independently, enabling scaling without requiring complex high-resolution lithography across the entire array. The selective opening technique removes material only in the PB region, simplifying the photolithographic process while maintaining the ability to accommodate increased bit density.
Solution Approach 2:
The patent segments the CuA region into distinct areas, specifically isolating the page buffer region from the rest of the circuit under array. By dividing the structure and applying different processing techniques to different segments (selective opening for PB, standard processing for other regions), the overall system complexity is reduced while still achieving the required scaling for higher bit density.
2Area of moving object
If high aspect ratio etches are performed to scale the page buffer, then the page buffer area can be reduced, but the etch depth control becomes more stringent and complex
Solution Approach 1:
The patent applies local quality by performing selective opening only in the page buffer region rather than uniformly across the entire structure. This localized approach allows for optimized etching parameters specific to the PB region, avoiding the need for high aspect ratio etches in other areas. The selective removal of material enables area reduction with relaxed etch depth control requirements compared to uniform high-aspect-ratio etching.
3Area of stationary object
If the page buffer area is scaled down to maintain zero-periphery architecture, then CuA space utilization improves, but the process complexity increases
Solution Approach 1:
The patent performs preliminary action by selectively opening the page buffer region before completing the full transistor formation process. This advance preparation allows subsequent steps to proceed with standard processing techniques, avoiding the need for complex high-resolution lithography and difficult-to-control etching operations that would otherwise be required to achieve the same scaling effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and cost of the process, improves cycle time, and achieves effective scaling of the page buffer area without the need for high aspect ratio etches, enabling more efficient use of CuA space and maintaining zero-periphery architecture.
Implementation Method 1
a dry etch to remove the blanket deposited conductive material
Data Source
AI summary
A variety of applications can include apparatus having a memory device structured with a circuit under array (CuA) architecture. A page buffer region in the CuA can be formed with a periphery region that is horizontally adjacent to the page buffer region. Contacts to gates for transistors in the page buffer region can be formed to land only on these gates, separating and electrically isolating the contacts and associated gates from each other in the page buffer region. Contacts to gates for transistors in the periphery region can be formed to land on conductive regions disposed on gates for transistors in the periphery region.