Page Buffer Circuit Pipeline for Faster IMC Multi-Bit MAC
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Solution Overview
Problem
The execution time for vector-vector-multiply (VVM) and multiply-accumulate (MAC) operations is significantly increased when performing multi-bit operations using in-memory-computing (IMC), necessitating an improved page reading and buffering mechanism to enhance efficiency and reduce execution time.
Innovation Solution
A page buffer circuit with latches, logic operation units, and a control circuit that performs logic operations on input and weight vectors, coupled with a pipeline operation mechanism to efficiently process page data stored in memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If in-memory-computing (IMC) is used for multi-bit operations, then computational capability is improved, but execution time is greatly increased
Solution Approach 1:
The patent divides the multi-bit operation into multiple single-bit operation cycles. Each bit position is processed separately through sequential read operations, where the memory array performs IMC for one bit position at a time, and results are accumulated across multiple cycles. This segmentation allows the system to maintain computational capability while managing execution time through parallel processing of different bit positions.
Solution Approach 2:
The patent performs preliminary actions by pre-charging bit lines and preparing sense amplifiers before actual read operations. Weight values are loaded into the memory array in advance, and control signals are pre-configured to enable rapid sequential access. This preliminary preparation reduces the overhead of each operation cycle and minimizes the total execution time for multi-bit operations.
2Productivity
If page reading mechanism is improved for efficiency, then data processing speed is increased, but device complexity is increased
Solution Approach 1:
The patent designs the page buffer circuit to perform multiple functions: it stores weight vectors, holds input vectors, accumulates computation results, and controls sequential read operations. The same hardware infrastructure (memory array, bit lines, sense amplifiers) is reused across multiple operation cycles for different bit positions, eliminating the need for separate dedicated circuits for each function and managing device complexity while maintaining high data processing speed.
Data Source
AI summary
A page buffer circuit adapted for a page-read device which including a memory array having several pages and several bit lines. The page buffer circuit comprises the following elements. First latches, receive a weight-vector from a corresponding one of the pages through the bit lines, and import an input-vector through a data input/output path. The weight-vector has a plurality of weight bit-data, and the input-vector has a plurality of input bit-data. Second latches, store the input bit-data of the input-vector. Logic operation units, coupled to the first latches to receive the weight bit-data, and coupled to the second latches to receive the input bit-data, perform a logic operation of the input bit-data and the weight bit-data to generate a logic operation result. The logic operation result is sent to one the first latches. A control circuit, selectively enables the logic operation units to perform the logic operation.