Page Buffer Latch Circuit Area Reduction

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Solution Overview

Problem

As the integration level of memory devices increases, the area occupied by page buffers in the peripheral circuit is limited, necessitating a reduction in the area and complexity of the page buffer to simplify the number of elements and reduce manufacturing costs.

Innovation Solution

The proposed solution involves a simplified circuit structure for the page buffer, which includes a bit line control circuit, a bit line discharging circuit, and a reduced number of latch circuits. This design reduces the number of electronic components and the space occupied by the page buffer, while also improving signal transmission stability and accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the integration level of memory devices is increased, then the storage capacity and performance are improved, but the area occupied by page buffers in the peripheral circuit increases

Engineering Contradiction:

Improvestorage capacityVSAvoidarea of page buffer

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The page buffer is divided into multiple latch circuits (first latch circuit, second latch circuit, third latch circuit, fourth latch circuit) that can independently store different data bits. This segmentation allows the page buffer to maintain high storage capacity while reducing the area of each individual latch circuit, thereby solving the contradiction between storage capacity and area occupation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple latch circuits are combined within a single page buffer structure, sharing common control circuits and signal transmission paths. This merging reduces the total area occupied by the page buffer while maintaining the ability to store multiple data bits, resolving the contradiction between storage capacity and area occupation.

Inventive Principle:

Principle #5Merging (Combining)

2Quantity of substance

If the number of latch circuits in the page buffer is increased to maintain data storage capability, then the data storage capacity is improved, but the device complexity and manufacturing cost increase

Engineering Contradiction:

Improvedata storage capacityVSAvoidcomplexity of page buffer

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The latch circuits in the page buffer are designed with universal structures that can store different data bits using the same circuit topology. This multi-functionality allows the page buffer to maintain high data storage capacity while reducing device complexity, as the same design pattern can be reused across multiple latch circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention optimizes the parameters of the latch circuits, such as the threshold voltages of transistors and the sizing of circuit components, to achieve efficient data storage with reduced complexity. By carefully adjusting these parameters, the page buffer can store multiple data bits while maintaining manageable device complexity and lower manufacturing costs.

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If the page buffer area is reduced to simplify manufacturing, then the manufacturing cost is reduced, but the signal transmission stability and accuracy may deteriorate

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidsignal transmission stability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The page buffer design transitions from a planar layout to a more compact three-dimensional arrangement of latch circuits and signal paths. This dimensional optimization allows the page buffer to maintain signal transmission stability and accuracy while occupying less area, thereby simplifying manufacturing without compromising reliability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The invention introduces carefully designed intermediate signal paths and control circuits that mediate between the reduced-size latch circuits and the rest of the memory system. These intermediary elements ensure that signal transmission stability and accuracy are maintained even as the overall page buffer area is reduced, resolving the contradiction between manufacturing simplicity and signal transmission reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250174279A1Page buffers and operation methods thereof, and memory devices and memory systems

Publication Date: 2025.05.29 YANGTZE MEMORY TECH CO LTD

AI summary

Examples of the present application relate to the field of semiconductors, and disclose a page buffer and an operation method thereof, a memory device and a memory system. The page buffer includes latch circuits, wherein the latch circuits includes: a latch control configuration circuit connected with a first data node and a second data node, and configure the first data node and the second data node to different logic levels respectively in response to a configuration signal, wherein a logic level of the first data node is opposite to a logic level of the second data node; and a latch transmission circuit connected with the first data node, the second data node, and a sense node, and configured to: couple the second data node with the sense node in response to a transmission signal, to transmit a configuration result of the latch control configuration circuit to the sense node.