Page Buffer Latch Configuration for Memory Storage
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Solution Overview
Problem
Current memory devices face limitations in enhancing functionality due to inefficient use of multiple latches in page buffers, which hinders the storage capacity and integration of data processing.
Innovation Solution
Incorporating an additional latch with changeable functions in the page buffer, allowing it to operate as a cache, sensing/forcing, or data keeper, depending on device settings, to enhance data programming speed and threshold voltage distribution characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple latches are included in the page buffer, then data storage capacity is increased, but latch utilization efficiency deteriorates
Solution Approach 1:
The additional latch is designed to perform multiple functions based on different operating modes. In the first mode, it stores program data alongside data latches. In the second mode, it stores sensing data or forcing data. In the third mode, it stores pass/fail information. This multi-functionality allows the latch to contribute to storage capacity while maintaining high utilization efficiency across different operational contexts.
Solution Approach 2:
The latch's functional role is dynamically changed based on the operating mode of the memory device. The control circuit selectively configures the additional latch to serve different purposes (data storage, sensing, forcing, or pass/fail indication) depending on the current operation requirements, thereby optimizing utilization efficiency while maintaining storage capacity.
2Reliability
If dedicated latches are allocated for each function, then functional reliability is improved, but device complexity increases
Solution Approach 1:
Instead of providing separate dedicated latches for each function (data storage, sensing, forcing, pass/fail), the invention uses a single additional latch that can be configured to perform any of these functions. The control circuit manages the latch's operational mode to ensure reliable function execution, thereby reducing overall device complexity while maintaining functional reliability.
Solution Approach 2:
The invention merges multiple potential latch functions into a single additional latch structure. By combining data storage, sensing, forcing, and pass/fail indication capabilities into one configurable latch, the design reduces the total number of latch components needed while maintaining the reliability of each function through controlled mode switching.
3Adaptability or versatility
If the additional latch is configured for multiple functions, then adaptability is improved, but control complexity increases
Solution Approach 1:
The control logic circuit dynamically adjusts the operational mode of the additional latch based on the current operation type. During program operations, the latch can be configured for data storage; during read operations, for sensing; during verification, for pass/fail indication. This dynamic reconfiguration provides high adaptability while the control logic manages complexity through mode-based selection rather than multiple dedicated control paths.
Data Source
AI summary
The memory device includes a page buffer circuit including a page buffer connected to each of a plurality of bit lines. The page buffer includes at least one additional latch and N number of data latches, and a control logic circuit that controls a setting of the page buffer. Based on a first setting, data programmed in a current program operation is stored in some of the N data latches and the at least one additional latch, and data which is to be programmed in a next program operation before the current program operation is completed is stored in some other of the N data latches and the at least one additional latches. Based on a second setting, externally provided data is not stored in the at least one additional latch in the current program operation and the next program operation.