Page Buffer Latch Modules for Parallel Data Writing
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Solution Overview
Problem
Current non-volatile memory devices face inefficiencies in data writing operations, particularly in managing multiple memory cells and handling data transmission, which affects overall system performance and data storage speed.
Innovation Solution
The implementation of a method involving a page buffer with m latch modules, each containing n latches, allows for parallel data writing and transmission across memory cells, utilizing pulses to change memory cell states and releasing latches to facilitate efficient data transfer between cell groups within the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written sequentially to memory cells one by one, then the control logic is simple, but the data writing time is long and storage speed is low
Solution Approach 1:
The page buffer is divided into multiple latch modules, with each latch module containing multiple latches that can independently store and write data to different memory cells. This segmentation allows parallel data writing operations across multiple memory cells simultaneously, significantly improving data writing speed while maintaining manageable control complexity through modular design
Solution Approach 2:
The patent transitions from sequential one-dimensional data writing to parallel multi-dimensional data writing by introducing multiple latch modules that can operate simultaneously. Each latch module handles different memory cells in parallel, effectively adding a temporal and spatial dimension to the data writing process, thereby increasing productivity
2Productivity
If latches are released frequently to enable parallel data transfer, then data writing efficiency improves, but control complexity increases
Solution Approach 1:
The control logic is designed to release latches in advance based on predetermined timing sequences and memory cell states, rather than reacting to each state change individually. This preliminary action approach enables efficient parallel data transfer while simplifying control by using pre-established rules for latch management
Solution Approach 2:
The control logic monitors the states of memory cells and uses this feedback information to determine when to release latches. By continuously monitoring cell states and adjusting latch release timing accordingly, the system achieves efficient parallel data transfer with automated control, reducing the complexity of manual latch management
Data Source
AI summary
The method of operating a non-volatile memory device includes dumping data stored in input latches of a page buffer to other latches of the page buffer to receive second data to be written to a second cell group of a memory cell array from outside the non-volatile memory device during writing of first data to a first cell group of the memory cell array. In the method, receiving of the second data may be finished before the writing of the first data is finished.