Page Buffer Circuit Parallel Latch Operations
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Solution Overview
Problem
Non-volatile memory devices face inefficiencies in data reading due to the time gap between sensing data from memory cells and outputting it, particularly in sequential and random read operations, which affects the overall performance and speed of data retrieval.
Innovation Solution
The implementation of a page buffer circuit with first and second page buffers, each containing sense latches, data latches, and cache latches, where the control logic circuit coordinates the dumping and transmission of data to minimize the time period between sensing and outputting, allowing simultaneous or staggered operations to enhance read efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is sensed and output sequentially through page buffer latches, then data integrity is maintained, but the time period from sensing to output increases
Solution Approach 1:
The page buffer circuit is divided into multiple independent latches (sense latch, data latch, cache latch) that can operate in parallel. Each latch handles a specific stage of data processing, allowing simultaneous sensing, latching, and transmission operations across different latch groups, thereby reducing the overall time period from sensing to output while maintaining data integrity through structured segmentation.
Solution Approach 2:
The sense latch performs preliminary data sensing and initial latching before the data latch and cache latch complete their operations. By preparing data in advance through the sense latch, the system enables overlapping execution stages where subsequent latches are already positioned to receive and transmit data, minimizing idle time and reducing the total sensing-to-output period.
2Productivity
If multiple page buffers operate simultaneously, then read efficiency improves, but control complexity increases
Solution Approach 1:
The page buffer circuit is divided into multiple independent latch groups (first page buffers with sense/data/cache latches, and second page buffers with similar structures). Each latch group can be independently controlled and operated in parallel, allowing simultaneous read operations across multiple buffers while maintaining organized, modular control that prevents excessive complexity.
Solution Approach 2:
The control logic circuit is prepared in advance to coordinate the timing and sequence of operations across multiple page buffers. By pre-establishing control signals that synchronize the sensing, latching, and transmission phases of different buffers, the system enables efficient parallel operation without requiring complex real-time arbitration, thus improving read efficiency while keeping control complexity manageable.
Data Source
AI summary
A non-volatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit, and a control logic circuit. The page buffer circuit includes a plurality of first page buffers and a plurality of second page buffers, each including a sense latch, a data latch, and a cache latch. The sense latch senses data stored in the memory cell array and dumps the sensed data to the data latch, the data latch dumps the data dumped by the sense latch to the cache latch, and the cache latch transmits the data dumped by the data latch to a data I/O circuit. While the cache latch included in at least one of the plurality of first page buffers is performing a data transmit operation, the data latch included in at least one of the plurality of second page buffers performs a data dumping operation.