Page Buffer Data Latch Reuse for Flash Memory Capacity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory devices, such as flash memory, face inefficiencies in data storage capacity due to underutilized data latches in page buffers, particularly during column repair operations, which are not used when no failures occur.
Innovation Solution
Implementing a memory device architecture that utilizes unused data latches in page buffers as a substitute for buffer memory, enhancing storage capacity by repurposing these latches for data storage operations even when no column repair is necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data latches in column repair cells are left unused, then the device complexity is reduced and ease of operation is maintained, but the storage capacity is wasted and productivity decreases
Solution Approach 1:
The data latches originally designed exclusively for column repair operations are made multi-functional by enabling them to serve as buffer memory during normal operations. The page buffer latch input/output circuit detects when data latches in non-repair page buffers are idle and dynamically allocates them for buffer memory functions, allowing the same hardware resources to fulfill multiple purposes throughout the device's operational lifecycle.
Solution Approach 2:
The system implements dynamic resource allocation where the function of data latches changes based on operational context. During column repair operations, data latches serve repair functions; during normal operations when not needed for repair, the same data latches are dynamically repurposed as buffer memory. This dynamic switching is managed through control logic that monitors latch usage status and reconfigures connections accordingly.
2Quantity of substance
If additional buffer memory is added to increase storage capacity, then the storage capacity is improved, but the physical space increases and device complexity increases
Solution Approach 1:
Instead of adding dedicated buffer memory hardware, the invention repurposes existing data latch resources to perform buffer memory functions. The same data latches that hold data for column repair operations are utilized as buffer memory during normal operations, eliminating the need for additional physical memory components and maximizing the utilization of already-present hardware resources.
Solution Approach 2:
The system recovers unused data latch resources from column repair page buffers and redeploys them as buffer memory. By identifying and utilizing idle data latches that would otherwise be discarded or left unused, the system effectively recovers valuable storage resources without requiring additional physical space or manufacturing complexity.
3Quantity of substance
If additional buffer memory is added to increase storage capacity, then the storage capacity is improved, but the manufacturing cost increases
Solution Approach 1:
The invention achieves increased effective storage capacity without additional manufacturing costs by making existing data latches multi-functional. The same data latch circuits are used for both their original column repair purpose and as buffer memory, eliminating the need to manufacture and integrate additional memory components, thereby avoiding associated costs for extra transistors, capacitors, and interconnect structures.
Solution Approach 2:
By recovering and utilizing idle data latch resources from column repair page buffers, the system avoids the manufacturing costs associated with producing and integrating additional buffer memory. The approach transforms previously wasted or underutilized hardware resources into functional buffer memory, achieving cost-effective capacity expansion without additional fabrication expenses.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory device (1100) includes a memory cell array (1110) configured to include a first memory cell for storing user data and a second memory cell for a column repair of the first memory cell; a page buffer circuit (1130) configured to include a first page buffer connected to the first memory cell and a second page buffer connected to the second memory cell; and a page buffer latch input/output circuit (2000) configured to use at least one data latch of the second page buffer as a substitute for a buffer memory (1300) during a data latch use operation.