Page Buffer Latch Sharing Data Transfer Node
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Solution Overview
Problem
As the demand for high-capacity memory devices with small size increases, the complexity of page buffer layouts and the integration of semiconductor elements becomes a challenge, limiting the design freedom and efficiency of memory devices.
Innovation Solution
The implementation of a page buffer design that includes a plurality of latches sharing a data transfer node, with a pass transistor connecting or disconnecting data transfer lines between page buffers, allowing for efficient data exchange and identification, and a control logic that manages these connections to optimize data transfer and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of memory devices is increased, then the capacity and small size are improved, but the layout complexity of conductive lines connected to page buffer semiconductor elements increases
Solution Approach 1:
The page buffer is divided into multiple latches (first latch, second latch, third latch, fourth latch) that can independently store data. Each latch is connected to bit lines through shared sensing nodes, allowing the page buffer to handle multiple bit lines with reduced conductive line complexity. This segmentation enables high integration by distributing data storage across multiple simple latch units rather than requiring a complex single-page-buffer structure.
Solution Approach 2:
Multiple latches share common sensing nodes (first sensing node, second sensing node) and data transfer nodes. For example, the first latch and second latch both connect to the first sensing node, which interfaces with a bit line. This merging of sensing nodes reduces the total number of conductive lines required, as one sensing node serves multiple latches, thereby reducing layout complexity while maintaining high integration capacity.
2Adaptability or versatility
If multiple latches share a data transfer node, then the design freedom is improved, but the data transfer efficiency may be affected
Solution Approach 1:
The page buffer dynamically controls the connection state of data transfer nodes between latches using control signals. The control logic can selectively connect or disconnect data transfer nodes based on operational requirements. For instance, during data transfer operations, the data transfer node connecting the first latch and second latch can be activated, while during monitoring operations, connections can be selectively maintained or disconnected. This dynamic control allows the system to optimize between design flexibility and data transfer efficiency for different operational modes.
Solution Approach 2:
Data transfer nodes act as intermediary elements between latches and between the page buffer and external circuits. The first data transfer node connects latches to each other, while the second data transfer node connects the page buffer to external circuits. These intermediary nodes allow selective data routing and transfer, enabling the page buffer to maintain design freedom while preserving data transfer efficiency by activating only the necessary data paths during operations.
3Productivity
If pass transistor connects data transfer lines between page buffers, then data exchange efficiency is improved, but power consumption increases
Solution Approach 1:
The pass transistor is activated periodically and selectively based on operational requirements rather than remaining continuously on. During monitoring operations, the pass transistor can be deactivated to reduce power consumption, while during data exchange operations between page buffers, it is activated to enable efficient data transfer. This periodic activation pattern allows the system to achieve high data exchange efficiency when needed while minimizing power consumption during idle or monitoring periods.
4Area of stationary object
If sensing node is shared between latches, then the area is reduced, but the reliability of data storage may be affected
Solution Approach 1:
Different sensing nodes are assigned to different functional groups of latches to maintain data integrity while reducing area. The first sensing node serves the first latch and second latch, while the second sensing node serves the third latch and fourth latch. Each sensing node maintains dedicated connections to its assigned latches, ensuring that data storage reliability is preserved within each group. This local quality assignment allows area reduction through sharing while maintaining reliability through dedicated sensing paths for each latch group.
Data Source
AI summary
A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.