Page Buffer Latch Sharing Data Transfer Node for Layout Efficiency
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Solution Overview
Problem
As the integration of memory devices increases, the complexity of conductive lines connected to page buffers in memory devices becomes a challenge, limiting design freedom and layout efficiency.
Innovation Solution
The implementation of a page buffer design that includes a plurality of latches sharing a data transfer node, with a pass transistor allowing connection or disconnection between data transfer nodes of different page buffers, and a control logic to manage data exchange and identification, enhancing the layout and design freedom of circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of memory devices increases, then the capacity and storage density are improved, but the area of regions occupied by page buffers decreases and the layout of conductive lines becomes increasingly complex
Solution Approach 1:
Multiple latches within a page buffer share a common data transfer node, merging previously separate signal paths into a unified structure. This reduces the number of independent conductive lines required and simplifies the overall layout while maintaining the ability to store and transfer data across multiple latches
Solution Approach 2:
The shared data transfer node serves multiple latches simultaneously, allowing a single conductive line to perform the data transfer function for several latches rather than requiring separate dedicated lines for each latch. This multi-functional approach reduces line complexity while preserving full operational capability
2Device complexity
If multiple latches share one data transfer node, then the layout efficiency and design freedom are improved, but the potential for data interference between latches increases
Solution Approach 1:
Pass transistors are introduced as dynamic switching elements that control the connection state of the shared data transfer node. These transistors can dynamically connect or isolate individual latches from the shared node based on operational requirements, providing active protection against data interference while maintaining the benefits of sharing during isolated operation
Solution Approach 2:
Pass transistors act as intermediary control elements between the shared data transfer node and individual latches. They mediate the data flow by selectively enabling or disabling connections, ensuring that data operations in one latch do not interfere with other latches while still allowing controlled sharing when needed
Data Source
AI summary
A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.