Page Buffer Latch Unit for Semiconductor Memory Cell Current Testing
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Solution Overview
Problem
The complexity of test circuits in semiconductor memory devices for measuring cell current leads to increased chip size due to the need for numerous circuits within page buffers during operational characteristic testing.
Innovation Solution
Implementing the necessary test circuits using the existing circuit of a page buffer, which includes a latch unit for storing data and coupling the bit line to a pad for test operations, thereby reducing the need for additional test-specific circuits and minimizing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional test circuits are added within page buffers to measure cell current, then measurement capability is improved, but device complexity and chip size increase
Solution Approach 1:
The latch unit in the page buffer is designed to serve dual purposes: storing data during normal memory operations and coupling the bit line to the pad for cell current measurement during test operations. This multi-functionality eliminates the need for separate dedicated test circuits within the page buffer, thereby maintaining measurement capability while reducing device complexity and chip size
2Measurement precision
If additional test circuits are added within page buffers to measure cell current, then measurement capability is improved, but chip size increases
Solution Approach 1:
The latch unit is configured to perform both data storage and test signal coupling functions. By utilizing the existing latch unit structure for test operations, the patent avoids adding separate test circuitry that would occupy additional chip area, thus maintaining measurement capability while minimizing chip size
3Device complexity
If existing page buffer circuits are utilized for test operations, then device complexity is reduced, but test operation capability may be limited
Solution Approach 1:
The latch unit is dynamically controlled through control signals to switch between normal data storage mode and test signal coupling mode. This dynamic reconfiguration allows the existing circuit to adapt to different operational requirements, maintaining both simplicity and test operation versatility
Data Source
AI summary
A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed into memory cells included in the cell string or for storing data read from the memory cells. Each of the page buffers is coupled to a pad for the test operation of the memory cells according to data stored in the latch unit in the test operation.